Semiconductor device manufacturing: process – Coating of substrate containing semiconductor region or of... – By reaction with substrate
Reexamination Certificate
1999-08-17
2001-08-21
Lee, Eddie C. (Department: 2815)
Semiconductor device manufacturing: process
Coating of substrate containing semiconductor region or of...
By reaction with substrate
C438S770000, C438S774000, C438S788000, C438S594000, C204S157970
Reexamination Certificate
active
06277765
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to microelectronic structures and fabrication methods, and more particularly to the formation of layers having low dielectric constants.
2. Background
Advances in semiconductor manufacturing technology have led to the development of integrated circuits having multiple levels of interconnect. In such an integrated circuit, patterned conductive material on one interconnect level is electrically insulated from patterned conductive material on another interconnect level by films of material such as silicon dioxide. Connections between the conductive material at the various interconnect levels are made by forming openings in the insulating layers and providing an electrically conductive structure such that the patterned conductive material from different interconnect levels are brought into electrical contact with each other. These structures are often referred to contacts or vias.
A consequence of having multiple layers of patterned conductive material separated by an insulating layer is the formation of undesired capacitors. The parasitic capacitance between patterned conductive material, or more simply, interconnects, separated by insulating material on microelectronic devices contributes to effects such as RC delay, power dissipation, and capacitively coupled signals, also known as cross-talk.
One way to reduce the unwanted capacitance between the interconnects is to use an insulating material with a lower dielectric constant. Various organic polymers have been used to form these insulating layers because their dielectric constants tend to be less than the dielectric constant of the most commonly used insulator, which is silicon dioxide. Unfortunately, organic polymers typically suffer from lower mechanical strength and hardness than silicon dioxide.
What is needed is an insulating layer that overcomes the deficiencies of organic polymer dielectric layers, while still providing low parasitic capacitance between interconnect layers, and methods of making such an insulating layer.
SUMMARY OF THE INVENTION
Briefly, a low dielectric constant material, suitable for use as an interlayer dielectric in microelectronic structures includes a porous silicon oxide layer.
In a further aspect of the present invention, a porous oxide of silicon is formed by the room temperature oxidation of porous silicon. A metal catalyzes the room temperature oxidation.
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Cheng Peng
Chiang Chien
Doyle Brian S.
Tran Mark Thiec-Hien
Brock II Paul E
Intel Corporation
Lee Eddie C.
Werner Raymond J.
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