Method for the fabrication of a doped silicon layer

Details Method for the fabrication of a doped silicon layer Method for the fabrication of a doped silicon layer

1999-09-03

2001-03-06

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Formation of semiconductive active region on any substrate

Fluid growth from gaseous state combined with subsequent...

Reexamination Certificate

active

06197666

ABSTRACT:

BACKGROUND OF THE INVENTION
Field of the Invention
The invention relates to a method for the fabrication of a doped silicon layer.
Low-impedance conductive elements are needed in a diversity of applications, for example as contacts or electrodes. Examples of such applications are a gate electrode of an MOS transistor in a CMOS configuration or a selector transistor in a DRAM, a contact for a bipolar transistor or a conductive connection between a selector transistor and a storage capacitor in a DRAM memory cell.
The use of conductive elements containing a silicide layer is known for applications of that kind (see, for example, a book entitled “Technologie hochintegrierler Schaltungen” [Technology of Large-Scale Integrated Circuits], by D. Widmann et al., Springer Verlag 1988, pages 95-96 and 215-216). The use of silicide requires additional equipment and it furthermore increases the costs of the fabrication process as a result.
SUMMARY OF THE INVENTION
It is accordingly an object of the invention to provide a method for the fabrication of a doped silicon layer, which overcomes the hereinafore-mentioned disadvantages of the heretofore-known methods of this general type and which can be used in the fabrication of low-impedance conductive elements as well as a microelectronic structure with a low-impedance conductive element.
With the foregoing and other objects in view there is provided, in accordance with the invention, a method for the fabrication of a doped silicon layer, which comprises depositing a silicon layer by using a process gas containing SiH
4
, Si
2
H
6
and a doping gas; and carrying out the deposition in a CVD reactor within a temperature range between 600° C. and 680° C. and within a pressure range between 100 torr and atmospheric pressure.
It was established that, in the method, the addition of Si
2
H
6
to a process gas containing SiH
4
and a doping gas promotes the incorporation of dopant into the deposited silicon layer. In this way lower resistivities are achieved in the deposited layer than would be the case when using a process gas containing SiH
4
and a doping gas. The addition of Si
2
H
6
also increases the rate of deposition. Thus the method achieves lower resistivities at higher deposition rates.
In accordance with another mode of the invention, the ratio of Si
2
H
6
to SiH
4
preferably has a value between 1:1.5 and 1:6. The ratio of Si
2
H
6
to SiH
4
is preferably 1:3 to 1:6. The doped silicon layer deposited according to this method is essentially polycrystalline.
In accordance with a further mode of the invention, an activation of the dopant preferably takes place through heat treatment after the deposition. The heat treatment is carried out in a temperature range between 1000° C. and 1200° C., preferably between 1050° C. and 1100° C.
In accordance with an added mode of the invention, the doped silicon layer is especially suitable as a starting material for the fabrication of a conductive element of doped silicon that has a resistivity less than or equal to 0.5 m&OHgr;cm at a layer thickness between 50 nm and 200 nm. In this case the ratio of Si
2
H
6
to SiH
4
during deposition is set at 1:3 to 1:6.
Due to its resistivity, the conductive element can be used as a gate electrode, a bipolar contact or a connection between electrical components. Due to the deposition rate of 50 nm per minute achieved in the method according to the invention, the conductive element can be fabricated inexpensively.
In accordance with an additional mode of the invention, the conductive element can be disposed on any required surface, especially on a level surface, above a step, or in a trench.
In accordance with a concomitant mode of the invention, when depositing the doped silicon layer above a step in a surface of a substrate, a good conformity is achieved in covering the edge of the step. The conformity, i.e. the ratio of the thickness of the layer at the essentially vertical surfaces to the thickness of the layer at the essentially horizontal surfaces, is at least 50 percent.
Other features which are considered as characteristic for the invention are set forth in the appended claims.
Although the invention is illustrated and described herein as embodied in a method for the fabrication of a doped silicon layer, it is nevertheless not intended to be limited to the details shown, since various modifications and structural changes may be made therein without departing from the spirit of the invention and within the scope and range of equivalents of the claims.
The construction and method of operation of the invention, however, together with additional objects and advantages thereof will be best understood from the following description of specific embodiments when read in connection with the accompanying drawings.


REFERENCES:
patent: 5700520 (1997-12-01), Beinglass et al.
patent: 5786027 (1998-07-01), Rolfson
patent: 59-052251 (1984-03-01), None
patent: 01109715 (1989-04-01), None
patent: 9410521 (1994-10-01), None
“Technologie hochintegrierter Schaltungen”, D. Widmann et al., Springer-Verlag, Berlin, Heidelberg, New York, London, Paris, Tokyo, 1988, pp. 95, 96, 215, 216.

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