Digital delay locked loop for reducing power consumption of...

Details Digital delay locked loop for reducing power consumption of... Digital delay locked loop for reducing power consumption of...

1997-12-18

2001-04-24

Tse, Young T. (Department: 2634)

Pulse or digital communications

Synchronizers

Phase displacement, slip or jitter correction

C327S142000, C327S153000, C327S161000

Reexamination Certificate

active

06222894

ABSTRACT:

This application corresponds to Korean patent applications No. 96-67415 and 96-67416, both filed Dec. 18, 1996 in the name of Samsung Electronics Co., Ltd. which are herein incorporated by reference for all purposes.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates generally to synchronous semiconductor memory devices driven in response to exterior system clocks, and more particularly, to digital delay locked loops which can reduce the power consumption of such synchronous semiconductor memory devices.
2. Description of the Related Art
A synchronous semiconductor memory device typically has a buffer for receiving an exterior system clock and generating an internal clock which is used in the interior of the chip to perform high-speed operations. Therefore, each device within the chip that receives the output from the buffer operates in synchronization with the system clock. However, since the buffer delays the system clock, a phase difference occurs between the external system clock and the internal clock. That is, the operation of the interior of the chip is delayed with respect to the external clock by this phase difference. Therefore, efforts have been made to devise a technique for operating the internal clock in complete synchronization with the external system clock.
One prior art method for eliminating the phase delay uses a phase locked loop (PLL), a delay locked loop (DLL), or other similar device to minimize the skew between the external system clock and the internal clock. However, this technique is not suitable for use with high-speed synchronous DRAM (Dynamic Random Access Memory) devices due to the long locking time for phase synchronization. This technique also increases the standby current consumed by the device while it is in a standby state. Furthermore, there are difficulties in operating a PLL or DLL at specific frequencies.
FIG. 1
shows another prior art scheme for reducing the skew between the external system clock and the internal clock in which a digital delay locked loop using a synchronous delay line (SDL) generates an internal clock which is accurately synchronized with the external system clock.
Referring to
FIG. 1
, a delay buffer BDC delays an external system clock CLK. A first clock PCLK_M generated by the delay buffer BDC is connected to the input node of a main delayer MDC, the input nodes of a plurality of phase delay detectors DDC
1
-DDCn, and the input node of a second synchronous delay line consisting of a plurality of unit delayers BUD
1
-BUDn. The output node of the main delayer MDC is connected to a plurality of unit delayers FUD
1
-FUDn each having the same delay length. The plurality of unit delayers FUD
1
-FUDn are connected to each other in series and form a first synchronous delay line. The plurality of unit delayers FUD
1
-FUDn within the first synchronous delay line delays a second clock D
1
, which is output from the main delayer MDC, and generates delayed clocks D
2
-Dn.
In the second synchronous delay line, the unit delayers BUD
1
-BUDn each have the same delay length as the unit delayers FUDi, where i=1 . . . n, and are serially connected. Switches SWC
1
-SWCn are connected between the input and output nodes of the unit delayers BUD
1
-BUDn and are arranged to selectively supply either the first clock PCLK_M or one of the a delayed clocks D
2
′-Dn′ to an output node as the internal clock signal PCLK in response to the activation one of a plurality of enable signals Fi which are output by the phase delay detectors DDCi where i=1 . . . n. The switches SWC
1
-SWCn receive, through their respective input terminals, the first clock PCLK_M and the delayed clocks Di′ generated by the unit delayers BUD
1
-BUDn of the second synchronous delay line, and are individually enabled by the activation of output signals from the phase delay detectors DDC
1
-DDCn. The phase delay detectors DDC
1
-DDCn latch the delayed clocks D
1
-Dn when the first clock PCLK_M switches to logic “LOW” and activate the enable signal Fi when PCLK_M is phase-synchronized with the delayed clock Di.
An example of the operation of
FIG. 1
will now be described with reference to
FIG. 2
which is a timing chart showing waveforms of various signals in the circuit of FIG.
1
. If the external system clock CLK shown in
FIG. 2
is applied, the delay buffer BDC generates the first clock PCLK_M which is delayed and level-converted to a clock pulse shown in FIG.
2
. The first clock PCLK_M is delayed by the main delay MDC having a delay length corresponding to the delay length of the delay buffer BDC and generated as the second clock D
1
. Moreover, the first clock PCLK_M generated by the delay buffer BDC is simultaneously supplied to the first input nodes of each of the phase delay detectors DDC
1
-DDCn and to the unit delayer BUD
1
of the second synchronous delay line. The second clock D
1
is sequentially delayed by the unit delayers FUD
1
-FUDn of the first synchronous delay line, which are serially connected to the output node of the main delayer MDC, and generated as delayed clocks D
2
-Dn. Each of the unit delayers FUD
1
-FUDn has the same delay length. The second clock D
1
generated by the main delayer MDC and the delayed clocks D
2
-Dn are supplied to the second input nodes of each of the phase delay detectors DDC
1
-DDCn.
The phase delay detector DDC
1
compares the phase of the first clock PCLK_M generated by the delay buffer BDC with the phase of the second clock D
1
generated by the main delayer MDC. Other phase delay detectors DDC
2
-DDCn compare the phase of the first clock PCLK_M generated by the delay buffer BDC with the phase of each of the delayed clocks D
2
-Dn generated at respective output nodes of the unit delayers FUD
1
-FUDn of the first synchronous delay line. The phase delay detectors DDC
1
-DDCn activate the enable signal Fi that has the same period as the delayed clock Di when the two clocks are phase-synchronized.
For example, if the first clock PCLK_M has the same phase as a delayed clock D
12
generated by unit delayer FUD
12
, phase delay detector DDC
12
latches the delayed clock D
12
and generates an enable signal during a logic “LOW” interval of the first clock PCLK_M. That is, the phase delay detector DDC
12
activates the output signal F
12
as indicated by waveform F
12
shown in FIG.
2
. Therefore, switch SWC
12
, which has a control terminal connected to the output node of the phase delay detector DDC
12
, is turned on, and a clock D
12
′ sequentially delayed by the unit delayers BUD
1
-BUD
11
is connected to the output node of the internal clock PCLK. In other words, by enabling the signal F
12
from the phase delay detector DDC
12
, the circuit of
FIG. 1
generates the internal clock from the output D
12
′ by delaying the first clock PCLK_M through the unit delayers BUD
1
-BUD
11
. In this case, the internal clock PCLK has no delay generated by the main delayer MDC.
The internal clock PCLK generated by the above-described operation is generated with the same phase as the external system clock CLK without any delay after two periods of the external system clock CLK. Since it takes a short time to equalize the phase between the external system clock CLK and the internal clock PCLK, the performance of a synchronous memory device can be improved by using a digital delay locked loop that has a synchronous delay line as shown in FIG.
1
.
The detailed construction of the digital delay locked loop of
FIG. 1
will now be described with reference to
FIG. 3
so that the preferred embodiments of the present invention, which will be described later on, can be more fully understood.
FIG. 3
is a circuit diagram showing more details of the unit delayers FUDD
1
-FUDn and BUD
1
-BUDn constituting the first and second synchronous delay lines, the switches SWC
1
-SWCn, the phase delay detectors DDC
2
-DDCn, and the mutual connection relationship therebetween, of the digital delay locked loop of FIG.
1
.
The delay buffer BDC indicated in
FIG. 1
is not shown in FIG

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