Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-12
2001-05-29
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S217000, C438S286000, C438S287000, C438S306000, C438S563000, C438S591000, C438S216000, C438S545000, C438S546000
Reexamination Certificate
active
06238985
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, specifically, to a semiconductor device and method of fabricating the same, which improves its driving power and reliability.
2. Discussion of Related Art
The MOS technology, where the surface of silicon is treated with a silicon oxide layer having good insulation characteristics, remarkably improves the transistor characteristic and transistor fabrication process. There are PMOS, NMOS and CMOS in MOS devices. At the earlier stage, the PMOS device is widely used because it has lower consumption power and its fabrication process is easily controlled during the manufacture of integrated circuit. However, in an integrated circuit requiring high speed, the NMOS device replace the PMOS. This is because the carrier (electron) mobility of the NMOS is faster than the carrier (hole) mobility of the PMOS device by approximately 2.5 times.
Though the CMOS device is fabricated through process more complicated than that for forming the PMOS or NMOS device, its consumption power is very low. Accordingly, the NMOS device is used for the memory region of a semiconductor device, and CMOS device is used for its periphery circuit. Meanwhile, the size of MOS device, especially, the channel length, is gradually reduced as the semiconductor device becomes highly integrated and high-speed. As a result, the distance between the source and drain is decreased but the device still uses the conventional power voltage of 5V. This increases the electric field intensity in the MOS device.
On the reduction of channel length, the carrier obtains high energy from the electric field while it moves from the source to the channel, and it's temperature when it reaches the drain is much higher than that of the lattice around it. Accordingly, impact ionization due to the carrier occurs. This becomes a problem in the NMOS device rather than in the PMOS because electrons are easily impact-ionized than holes. Among electron-hole pairs generated from the impact ionization, the electrons move to the drain of n-type impurity region but holes move to the substrate of p-type impurity region in the NMOS device. The flow of holes creates substrate current. Some holes move to the source, so that the p-n junction becomes forward-biased, creating NPN transistor. This increases the amount of current, and thus impact ionization effect is raised, resulting in high drain current.
When the carrier in the channel is accelerated by the high electric field around the drain, and thus its energy becomes higher than the energy barrier between the substrate and gate oxide layer, the carrier becomes hot electron and is inserted into the gate oxide layer. The electron or hole inserted into the gate oxide layer is trapped in the gate oxide layer, and forms a potential on the interface between the substrate and gate oxide layer. This changes the threshold voltage, or decreases mutual conductance. This phenomenon is called hot carrier effect, which is resulted from the high electric field generated at the pinch-off region around the drain. To improve the hot carrier effect, an LDD structured MOS transistor has been proposed, in which a low concentration layer having a gentle impurity concentration profile is formed between the drain and channel, to decrease the high electric field.
With this LDD structure, a self-aligned lightly doped impurity region (LDD region) is located between the channel region, and heavily doped impurity regions (source and drain regions) placed on both sides of the channel region. The LDD region spreads the high electric field around the drain junction. Thus, the carrier supplied from the source is not rapidly accelerated even with a high voltage. This solves the hot carrier problem. However, the resistance of the LDD region serves as parasitic resistance because the concentration of the LDD region is lower (approximately {fraction (1/1000)}) than that of the source and drain regions, resulting in reduction of driving current. The increase in the impurity concentration of the LDD region raises the substrate current, heightening the hot carrier effect. However, the reduction of the LDD region's concentration decreases the driving current under the influence of the parasitic resistance.
Accordingly, it is required that the concentration of the LDD region is high, and easily controlled. There is a method to meet this requirement, in which the LDD region is formed on both sides of a gate electrode through ion implantation using the gate electrode as a mask, sidewall spacers are formed on the sides of the gate electrode using an oxide layer, and ion implantation is carried out using the sidewall spacers and gate electrode as a mask, to form heavily doped source and drain regions. With this LDD structure, the LDD region is formed on the source side as well as drain side. As a result, the LDD region formed between the heavily doped source region and channel region creates higher sheet resistance, and increases the total resistance of the channel. This brings about the reduction in the driving current of MOS device, deteriorating the driving power of MOS transistor.
In addition to, there is a MOSFET structure having a pocket region which is deeply formed around the channel, and surrounds the LDD region of the source and drain regions, to thereby prevent punchthrough. A conventional method of fabricating the semiconductor device described above is explained below with reference to the attached drawings.
FIGS. 1A
to
1
F are cross-sectional views showing a method of fabricating the conventional MOSFET.
Referring to
FIG. 1A
, a gate oxide layer
2
and polysilicon layer
3
are sequentially formed on a p-type semiconductor substrate
1
, photoresist is coated on polysilicon layer
3
and patterned through exposure and development, to define a gate electrode formation region. Referring to
FIG. 1B
, polysilicon layer
3
and gate oxide layer
2
are selectively removed through etching process using the patterned photoresist as a mask, to form a gate electrode
3
a.
Referring to
FIG. 1C
, n-type lightly doped impurity regions
4
are formed on predetermined portions of p-type semiconductor substrate
1
, placed on both sides of gate electrodes
3
a
, by ion implantation using gate electrode
3
a
as a mask. This impurity region
4
corresponds to a conventional LDD region, which prevents the hot carrier effect due to impact ionization. Lightly doped impurity regions
4
are symmetrically formed in the portions of semiconductor substrate
1
, placed on both sides of gate electrode
3
a
. Furthermore, lightly doped impurity regions
4
are diffused in the substrate during ion implantation and heat treatment, thereby being superposed on a predetermined portion of gate electrode
3
a.
Referring to
FIG. 1D
, p-type lightly doped impurity regions
5
are formed in predetermined portions of semiconductor substrate
1
, placed on both sides of gate electrode
3
a
, through tilt ion implantation using gate electrode
3
a
as a mask, and heat treatment. Here, p-type lightly doped impurity regions
5
are formed deeper than n-type lightly doped impurity regions
4
, thus surrounding n-type regions
4
. Referring to
FIG. 1E
, an oxide layer is formed on the overall surface of the substrate including gate electrode
3
a
, and etched back, to form sidewall spacers
6
on both sides of the gate electrodes.
Referring to
FIG. 1F
, n-type heavily doped impurity regions
7
are formed in predetermined portions of substrate
11
, placed on both sides of gate electrode
3
a
and sidewall spacer
6
, through high-concentration impurity ion implantation using gate electrode
3
a
and sidewall spacer
7
as a mask, and heat treatment, thereby accomplishing a MOSFET having a pocket shaped LDD region, in which p-type lightly doped impurity region
5
having a conductivity is identical to that of the substrate surrounds n-type lightly doped region
4
whose conductivity is opposite to that of the substrate.
There are problems in th
Fourson George
Garcia Joannie A.
LG Semicon Co. Ltd.
Morgan & Lewis & Bockius, LLP
LandOfFree
Semiconductor device and method for fabricating the same does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Semiconductor device and method for fabricating the same, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Semiconductor device and method for fabricating the same will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2494687