Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-26
2001-01-23
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S255000
Reexamination Certificate
active
06177308
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 88104982, filed Mar. 30 1999, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method for manufacturing the capacitor of a semiconductor memory cell. More particularly, the present invention relates to a method for manufacturing the stacked capacitor of dynamic random access memory (DRAM).
2. Description of Related Art
As semiconductor device manufacturing progresses into the deep sub-micron range, dimensions of each semiconductor are all reduced. One consequence of this is the reduction of space for accommodating a capacitor. In contrast the size of software needed to operate a computer is forever growing, and hence the needed memory capacity must be increased. In the presence of these conflicting requirements, some changes have to be made regarding the design of DRAM capacitors.
A stacked capacitor structure is the principle type of capacitor to be used in manufacturing semiconductor memory. The stacked type of capacitor has been used for quite some time and continues to be used, even in deep sub-micron device fabrication.
A Stacked capacitors can be roughly classified into crown-shaped, fin-shaped, cylinder-shaped or spread-out type. Although any of these stacked capacitors is able to satisfy the high density requirement of DRAMs, simply using such conventional structures to fabricate the capacitor can hardly go beyond 256 megabit (Mb) memory capacity.
Capacitance, however, can be increased by increasing the surface area of the lower electrode of, say, a crown-shaped capacitor so that higher memory capacity becomes possible. For example, the surface area of the lower electrode can be further increased by growing hemispherical grains (HSGs) on the lower electrode surface.
FIGS. 1A through 1E
are cross-sectional views showing the progression of manufacturing steps in fabricating a conventional double-sided crown-shaped capacitor.
First, as shown in
FIG. 1A
, a substrate
100
having a number of devices (not shown) thereon is provided. Next, a silicon oxide layer
102
and a silicon nitride layer
104
are sequentially formed over the substrate
100
. The silicon oxide layer
102
serves as an inter-layer dielectric (ILD) while the silicon nitride layer
104
serves as an etching stop layer during the fabrication of the double-sided crown-shaped capacitor. Both the silicon oxide layer
102
and the silicon nitride layer
104
can be formed using a chemical vapor deposition (CVD) method, for example.
Thereafter, photolithographic and etching operations are conducted to form a contact opening
106
that passes through the silicon oxide layer
102
and the silicon nitride layer
104
. Next, a doped polysilicon plug is formed inside the contact opening
106
. The doped polysilicon plug can be formed by first depositing a layer of doped polysilicon (not shown in the figure) over the silicon nitride layer
104
and filling the contact opening
106
using a chemical vapor deposition (CVD) method. Then, the doped polysilicon layer above the silicon nitride layer
104
is removed using, for example, a reactive ion etching (RIE) method.
Next, as shown in
FIG. 1B
, an insulation layer
108
is formed over the silicon nitride layer
104
. The insulation layer
108
can be formed using, for example, a chemical vapor deposition (CVD) method. The insulation layer
108
is made, for example, from borophosphosilicate glass (BPSG). Thereafter, an opening
110
that exposes the contact opening
106
is formed using photolithographic and etching techniques.
Next, as shown in
FIG. 1C
, an amorphous silicon layer
112
conformal to the opening
110
and surrounding areas is formed. The amorphous silicon layer
112
is formed using, for example, a low-pressure chemical vapor deposition (LPCVD) method.
Next, as shown in
FIG. 1D
, using the insulation layer
108
as an polishing stop layer, the amorphous silicon layer
112
above the insulation layer
108
are removed. Hence, only the amorphous silicon layer
112
inside the opening
110
remain. The method of removing portions of the amorphous silicon layer
112
includes a chemical-mechanical polishing (CMP) method.
Next, as shown in
FIG. 1E
using the silicon nitride layer
104
as an etching stop layer the insulation layer
108
above the silicon nitride layer
104
is removed using a wet etching method, for example. Hence, a crown-shaped capacitor structure is obtained.
Thereafter, selective hemispherical grains are formed on the exposed amorphous silicon surface. Next, dielectric material is deposited to form a capacitor dielectric layer, and then an upper electrode is formed over the capacitor dielectric layer to form the double-sided crown-shaped capacitor. Since subsequent operations should be to familiar to those skilled in the art of semiconductor manufacture, detailed descriptions are omitted here.
However, the silicon nitride layer
104
to be used as an etching stop layer during the removal of the insulation layer
108
can be easily turned into a surface with hemispherical grains in the selective hemispherical grain growing process. Since the presence of hemispherical grains on the surface of the silicon nitride layer
104
is highly undesirable, the hemispherical grains must be removed, causing additional processing complexity and yield reducibility.
FIGS. 2A and 2B
are cross-sectional views showing the structure before and after an operation for removing the native oxide from a conventional contact opening just before forming a barrier metal and a tungsten plug inside.
First, as shown in
FIG. 2A
, due to a capacitor processing requirements, two sides of a high aspect ratio (VIAR) contact opening
200
may include two silicon oxide layers
202
a
and
202
b
sandwiched between a silicon nitride layer
204
, instead of just the two silicon oxide layers
20
a
and
202
b.
In
FIG. 2B
, a cleaning operation for removing native oxide on the exposed surface
208
of the substrate
206
is carried out before forming a barrier metal and a tungsten plug inside the contact opening
200
so that reliability of the subsequently formed a metal plug can be maintained.
However, the silicon nitride layer
204
usually has an etching rate that differs from the two silicon oxide layers
202
a
and
202
b
. Consequently, after the native oxide removing process, protrusion of the silicon nitride layer
204
from the sidewalls of the contact opening
200
may result, thereby leading to difficulties in producing an uniform titanium and titanium nitride barrier metal in subsequent process.
In light of the foregoing, there is a need to improve the method of manufacturing double sided crown-shaped capacitor.
SUMMARY OF THE INVENTION
Accordingly, the purpose of the present invention is to provide a method of manufacturing a stacked capacitor that utilizes a silicon nitride layer as an etching stop layer for the removal of an insulation layer on each side of the crown-shaped lower electrode structure. In addition, a special high temperature oxide (HTO) that cannot form any hemispherical grain on its surface when selective hemispherical grains are grown on an amorphous silicon layer is used in place of the conventional silicon nitride layer. Hence, the present invention resolves the problem of forming hemispherical grains on the surface of a silicon nitride layer when it is used as an etching stop layer.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of forming stacked capacitor. The method includes the steps of providing a substrate. and then forming a inter-layer dielectric layer over the substrate. Next, a contact opening is formed in the inter-layer dielectric layer, and then a conductive plug is formed inside the contact opening. Thereafter, an etching stop layer is formed over the so inter-layer dielectric layer, an
Huang Jiawei
J.C. Patents
Tsai Jey
Worldwide Semiconductor Manufacturing Corp.
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