Method of forming capacitor with a HSG layer

Details Method of forming capacitor with a HSG layer Method of forming capacitor with a HSG layer

1998-10-01

2001-01-30

Fahmy, Wael (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S491000, C438S398000, C438S390000, C438S252000, C438S253000, C438S396000

Reexamination Certificate

active

06180451

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87110435, filed Jun. 29, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a capacitor, and more particularly, to a method of selectively forming a hemispherical grain (HSG) on a dynamic random access memory (DRAM) capacitor.
2. Description of the Related Art
In a DRAM, the typical method to access data is by charging or discharging optionally into each capacitor of the capacitor array on the semiconductor substrate.
Due to the higher and higher integration of an integrated circuit (IC), dimensions of devices or structures (such as transistors, capacitors) become smaller and smaller. Thus, in a conventional planar capacitor, the storage of charges (that is, the capacitance) decreases. The decrease of charge storage causes various problems, including mechanical deterioration and charge leakage by the larger susceptibility, and therefore, causes potential loss. The charge leakage caused by larger susceptibility may cause more frequent refresh period, and by which, memory can not handle data saving and reading properly. Moreover, the decrease of charge storage may need more complex data reading plan, or more sensitive charge induction amplifier.
It has been a trend of fabricating a DRAM with a capacitor having an improved storage capacitance. However, as the dimension of the memory cell shrinks due to the requirement of high integration, the lateral area of the capacitor becomes smaller and smaller. To maintain the capacitance, or even to increase the capacitance of the capacitor of a DRAM, a three dimensional capacitor which extends vertically in surface area is developed. Another method to increase to the capacitance of a DRAM capacitor is to select a dielectric material with a higher dielectric constant.
Recently, a method of forming a hemispherical grain of the bottom electrode of a capacitor to increase the surface area has been developed to increase the capacitance.
A conventional method of forming a DRAM capacitor with a hemispherical grain structure is shown in
FIG. 1A
to FIG.
1
B. In
FIG. 1A
, at least a metal-oxide semiconductor device (MOS) comprising a gate
102
and a source/drain region
104
is formed on a semiconductor substrate
100
. An oxide layer
106
is formed on the substrate
100
. Using photolithography and etching, a contact
108
is formed to penetrate through the oxide layer
106
and couple with the source/drain region
104
. An amorphous silicon layer is formed on the oxide layer
106
and the contact
108
. To increase the conductivity, the amorphous silicon layer is doped with wither N-type or P-type ions. The amorphous silicon layer is then patterned as denoted as
110
in the figure.
In
FIG. 1B
, in a high vacuum ambient at about 550° C. to 670°, the amorphous silicon layer
110
is annealed to crystallize. The amorphous silicon layer
110
is thus transformed into a poly-silicon layer
110
a
with a hemispherical grain structure
112
on the surface area. The poly-silicon layer
110
a
is then doped with ions to increase the conductivity.
The capacitor formed by the above conventional method has an increased surface area, and therefore, a larger capacitance is obtained. However, the dopant concentration near the surface of the hemispherical grain structure
112
is usually low. As shown in
FIG. 2
, an enlarged cross section view of the hemispherical grain structure is shown. By the conventional method, the doped ions are non-uniformly distributed. The surface dopant concentration
200
is lighter than the dopant concentration in the interior portion
202
. The insufficient surface dopant concentration near of the hemispherical grain causes a low conductivity. While applying the hemispherical grain structure to a high density DRAM, a depletion region is formed which block the current flow. The capacitor is thus degraded.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of forming a DRAM capacitor with a hemispherical grain structure. By introducing the DRAM device into a dopant contained ambient to perform an anneal process, the dopant is evenly distributed in the hemispherical grain structure, so that the hemispherical grain structure has a uniform dopant concentration. Using rapid thermal process (RTP) for the anneal process, an economic thermal budget is obtained. The small thermal budget is advantageous to sub-quarter micron very large scaled integration (VLSI) technologies.
To achieve the above-mentioned object and advantages, a method of forming a capacitor is provided. A semiconductor comprising a metal-oxide semiconductor is provided. The metal-oxide semiconductor comprises a gate and a source/drain region. An insulation layer is formed on the substrate to cover the gate and the source/drain region. A contact plug is formed to penetrate through the insulation layer and to couple with the source/drain region. A dope amorphous silicon layer is formed on the insulation layer and the contact plug. The amorphous silicon layer is defined to form a required patterned. The substrate is disposed in a vacuum ambient at about 550° C. to 670° C. for annealing to crystallize the amorphous silicon layer. The amorphous silicon layer is thus transformed into a poly-silicon layer. Meanwhile, a hemispherical grain structure is formed on the surface of the poly-silicon layer. The substrate is disposed in a dopant contained ambient at about 700° C. to 1000° C. for another annealing process. A dielectric layer is formed on the poly-silicon layer. Another poly-silicon layer is formed on the dielectric layer.
In addition to the application as a DRAM capacitor, a capacitor formed by the method according to the invention can also applied to other structures of a semiconductor substrate. Furthermore, the hemispherical grain structure
312
with a uniform dopant concentration can not only applied in forming a DRAM capacitor, but also can be applied in any structure which needs an increased surface area with a good conductivity.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.


REFERENCES:
Wolf, S.; Tauber, R. N.; Silicon Processing For The VLSI Era, vol. 1; Lattice Press; Sunset Beach, Ca.; 1986; pp. 261-265.

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