Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-22
2001-06-05
Bowers, Charles (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S269000, C438S270000
Reexamination Certificate
active
06242310
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to integrated circuits and more particularly to an improved method and structure which reduces the size of semiconductor devices.
2. Description of the Related Art
Integrated circuit devices are continually being made smaller in order to increase speed, make the device more portable and to reduce the cost of manufacturing the device. However, certain designs have a minimum feature size which cannot be reduced without compromising the integrity of electrical isolation between devices and consistent operation of the device.
For example, dynamic random access memory devices (DRAMs) which use planar metal oxide semiconductor field effect transistors (MOSFETs) with deep trench (DT) storage capacitors have a minimum features size of approximately 0.15 &mgr;m. Below that size, the internal electric fields exceed the upper limit for storage node leakage which decreases retention time below an acceptable level. Therefore, there is a need for different methods and/or different structures to further reduce the size of integrated circuit devices.
SUMMARY OF THE INVENTION
It is, therefore, an object of the present invention to provide a structure and method for forming an integrated circuit memory device. The method includes forming a conductor in a trench, forming an isolation collar along a perimeter of an upper portion of the trench conductor, forming supporting spacers above the isolation collar, forming a sacrificial layer between the supporting spacers along an upper surface of the trench conductor, forming an insulator above the sacrificial layer, forming a gate conductor above the insulator, removing the sacrificial layer to form a gap between the insulator and the trench conductor (wherein the supporting spacers maintain a relative position of the gate conductor, the insulator and the trench conductor) and forming a conductive strap in the gap.
The trench is formed in a substrate and the method further includes removing a portion of the substrate to expose a sidewall of the gate conductor, the insulator and the sacrificial layer. The removing of the sacrificial layer includes applying a selective plasma or chemical wet etch which removes the sacrificial layer and does not remove the gate conductor or the insulator.
The forming of the conductive strap includes depositing a conductive material in the gap and along sidewalls of the gate conductor and the insulator and oxidizing the conductive material to change the conductive material to an insulator material along the sidewalls of the gate conductor and the insulator while the conductive material remains conductive in the gap to form the strap. The conductive material includes an impurity and the oxidizing releases the impurity from the conductive material to the substrate to create a diffusion region.
Before the forming of the strap, the invention can include forming an insulating spacer material on a sidewall of the gate conductor. Additionally, the method includes, before the forming of the strap, forming a gate oxide layer in the trench.
REFERENCES:
patent: 6063657 (2000-05-01), Bronner et al.
Divakaruni Ramachandra
Mandelman Jack A.
Bowers Charles
Brewster William M.
International Business Machines - Corporation
Li Todd M.C.
McGinn & Gibb PLLC
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