Semiconductor memory device having silicon-on-insulator...

Details Semiconductor memory device having silicon-on-insulator... Semiconductor memory device having silicon-on-insulator...

1999-05-26

2001-09-25

Fourson, George (Department: 2823)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S350000

Reexamination Certificate

active

06294806

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of making a semiconductor device, and more particularly to a semiconductor memory cell fabricated on a silicon-on-insulator (hereinafter referred to SOI) type substrate.
BACKGROUND OF THE INVENTION
Substrates usefull in manufacturing semiconductor devices are increasingly required to possess a higher degree of freedom when designing a device to be fabricated thereon. Therefore, this trend has drawn more attention to the substrates of so called SOI type, which typically comprise a bonded wafer being structured such that a thermally grown oxide layer is sandwiched between two silicon wafers, at least one of the silicon wafers being mono-crystalline. The bonded wafer may be used for making an electric device such as a semiconductor device or, for example, a micro machine in one of the other fields of application. A transistor built on the SOI has an advantage of requiring low supply voltage and low operation voltage due to reduced well and load resistance. In addition, the SOI transistor exhibits high operation speed.
However, the SOI transistor has some inherent drawbacks. One important shortcoming of these SOI transistors is the occurrence of the floating body effect, or electrical floating. The electrical floating of the transistor active region allows the unstable characteristics of the transistors and generates reliability concerns associated with transistor mis-operation and degradation of the characteristics.
FIG. 1
schematically illustrates a DRAM device built on an SOI. The DRAM device typically includes a reversed capacitor
20
and word lines
14
a
and
14
b
, respectively formed on first insulating layer
22
and second insulating layer
18
which are disposed over a handling wafer
24
in this order. A device isolation layer
12
defines an active and an inactive region. The reversed capacitor
20
is connected to one of the source/drain regions
16
through the second insulating layer
18
. The other of the source/drain regions
16
is connected to a bit line
28
at a selected portion while other areas are insulated from the other source/drain regions
16
by a third insulating layer
26
formed therebetween. An area underlying the word line
14
a
and between the pair of the source/drain regions
16
is defined as a channel area. A fourth insulating layer
30
is disposed over the bit line
28
and metal lines
30
a
and
30
b
are formed on the fourth insulating layer
30
.
As can be seen, the channel area is in the state of electrical floating. Such a floating state of the channel area allows an irregular variation of the threshold due to an accumulation hole. Thus, there exists a need to develop a semiconductor memory device having an SOI structure that does not suffer from the drawbacks associated with electrical floating.
SUMMARY OF THE INVENTION
The present invention was made in view of the above problem, and it is therefore a feature of the present invention to provide a method for fabricating a DRAM device on an SOI type substrate wherein a channel area of the transistor is electrically connected to a conductor so as to suppress the floating body effect.
In accordance with a primary feature of the present invention, there is provided a method of fabricating a semiconductor device comprising providing a processing wafer having first and second surface opposing each other, forming a device isolation layer in and on the first surface of the processing wafer to define active and inactive regions, forming a gate electrode structure being composed of a gate oxide, a gate electrode and a pair of source/drain region on the active region, forming a first insulating layer on the gate electrode structure and on the first surface of the processing wafer, bonding one surface of a handling wafer onto the first insulating layer, and forming a second insulating layer on the second surface of the processing wafer. A conductor may be further formed on and in the second insulating layer so as to be electrically connected to the processing wafer underlying the gate electrode and between the pair of source/drain region. A second gate electrode may also be formed on the second insulating layer in alignment and parallel with and over the gate electrode.
In accordance with another feature of the present invention, there is provided a DRAM device on an SOI type substrate where the conductor connected to the channel area is aligned over the gate line and is parallel thereto. The conductor also is connected to the overlying metal line at the terminal portion of the cell array (i.e., around the sense amplifier). The accumulation hole caused by the floating body effect of the transistor flows out to the ground and the back-bias voltage (V
bb
) through the conductor connected to the channel to thereby prevent the subthreshold voltage leakage and suppress an unacceptable variation in the threshold voltage.
In accordance with yet another feature of the present invention, a device isolation region is formed on a semiconductor substrate or a processing wafer, and preferably the device isolation region surrounds active regions in and on one surface of the semiconductor substrate or processing wafer. A transistor including a gate oxide layer, a gate electrode, a capping layer, a pair of source/drain regions, and a channel area disposed between the pair of source/drain regions can be formed on the selected active region. A first insulating layer then may be formed on the transistor and over the semiconductor substrate or processing wafer. A capacitor then preferably is formed in a conventional manner on the first insulating layer and electrically connected to one of the source/drain region through the first insulating layer. A second insulating layer may be formed on the first insulating layer. A handling wafer then can be bonded onto the second insulating layer. The other surface of the semiconductor substrate or processing wafer preferably is ground and/or polished down to the device isolation region so that a bonded SOI type substrate is formed. A third insulating layer then can be formed on the polished semiconductor surface/processing wafer. A contact preferably is opened in the third insulating layer to the channel area of the transistor. A conductive material then can be deposited on the third insulating layer and in the contact opening and patterned to form a conductor line. A fourth insulating layer can be formed on the conductor line and over the third insulating layer. A bit line then may be formed on the fourth insulating layer and electrically connected to another source/drain region through selected fourth insulating layer. A fifth insulating layer then may be formed over the fourth insulating and a first metal line formed thereon.
According to another aspect of the present invention, the conductor line can be connected to the underlying gate line. Due to this connection between the gate line and the conductor line, the dynamic threshold voltage (V
t
) is controlled. If the gate current is zero (i.e., off current), channel current is submitted to zero concurrently, and consequently, the sub-threshold leakage is suppressed. On the other hand, if the gate current increases to a predetermined voltage (i.e., on current), the channel voltage also increases to that magnitude, so that V
t
of the channel significantly decreases and increases motility.
According to another aspect of the present invention, after formation of the third insulating layer, a second gate line can be formed on the third insulating layer and parallel to the underlying embedded gate line. The two gate lines then may be connected to each other. One of the two gate electrodes serves as a backgate and operates as described above.


REFERENCES:
patent: 5721444 (1998-02-01), Oashi et al.
patent: 5952694 (1999-09-01), Miyawaki et al.
patent: 6043535 (2000-03-01), Houston
patent: 6043536 (2000-03-01), Numata et al.
patent: 6063686 (2000-05-01), Masuda et al.
patent: 6100567 (2000-08-01), Burr
patent: 6111280 (2000-08-01), Gardner et al.

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