Field leakage by using a thin layer of nitride deposited by...

Details Field leakage by using a thin layer of nitride deposited by... Field leakage by using a thin layer of nitride deposited by...

1999-02-01

2001-04-03

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S362000, C438S439000, C257S506000, C257S510000, C257S640000, C257S647000, C257S649000

Reexamination Certificate

active

06211022

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to materials and methods used in the manufacture of a semiconductor device which includes an array of transistors to decrease current leakage to achieve better isolation between transistors.
2. Description of the Related Art
FIG. 1
shows a cross section of two NMOS transistors illustrating the typical configuration of materials used in the manufacture of a semiconductor device containing an array of transistors. The transistors are shown formed in a p-type silicon substrate
2
. A first transistor
4
includes n-type source and drain implant regions
6
and
8
provided in the substrate
2
. A polysilicon gate region
10
of the first transistor
4
is provided bridging the source
6
and drain
8
regions. The polysilicon gate region
10
is separated from the substrate
2
by a dielectric
22
. A second transistor
14
includes n-type source and drain implant regions
16
and
18
provided in the substrate
2
. A polysilicon gate region
20
of the second transistor
14
bridges the source and drain regions
16
and
18
.
A field oxide region
24
is provided in the substrate
2
separating region
8
of the first transistor
4
and region
16
of the second transistor
14
. The field oxide region
24
is provided to prevent field leakage between region
8
of the first transistor
4
and region
16
of the second transistor
14
. A polysilicon layer
26
overlies at least a portion of the field oxide region
24
. The polysilicon region
26
extends to serve as the gate region for other transistors (not shown) in the array, as do polysilicon regions
10
and
20
.
A dielectric region
22
surrounds at least a portion of the polysilicon gate regions
10
and
20
and overlies the polysilicon region
26
. The dielectric layer
22
can be composed of silicon dioxide, phosphorous silicate glass (PSG), tetraethyl orthosilicate (TEOS), borophosphorous tetraethyl orthosilicate (BPTEOS), or a combination of these materials. Although not shown, other layers of materials are applied above the dielectric layer
22
to complete fabrication of the array of transistors. For example, a metal layer can be provided above the dielectric layer
22
to provide an electrical connection to polysilicon gate regions
10
,
20
and
26
.
The threshold of a transistor, or gate to source voltage required to turn on the transistor, can be controlled by increasing the distance between the source and drain regions. When a high threshold for a transistor is desired, such as 12 volts or higher, leakage current beneath the field oxide region separating two transistors can significantly affect how wide the separation between source and drain regions of a transistor needs to be for a desired threshold. To prevent increased separation between source and drain regions of a transistor with leakage current beneath the field oxide region, the width of the field oxide region separating source and drain regions of two transistors can be increased.
Current leakage beneath the field oxide region can result when H
+
or Na
+
ions from layers deposited above the field oxide region penetrate into the field oxide region. The H+ or Na+ ions in the field oxide layer cause a migration of ions from the p-substrate underlying the field oxide region so that the p-substrate inverts and effectively acts like an n-type substrate. With inversion of the p-substrate beneath the field oxide region, significant current leakage between source and gate regions, such as regions
8
and
16
of
FIG. 1
, can result.
For a large array of transistors where it is typically desirable to increase the density of transistors in a given area, increasing the distance between source and drain regions of transistors, or increasing the width of the field oxide regions to overcome the effects of current leakage beneath the field oxide region is undesirable. Further, when high threshold voltages are desired, charge pump circuitry is typically used to pump voltage above a 5V Vcc input pin to 12 volts or higher to turn on particular transistors. With significant current leakage, charge pump circuitry provided on the chip must be increased in size to supply necessary voltages.
It is, thus, desirable to take steps to reduce leakage current beneath the field oxide region separating transistors in an array.
SUMMARY OF THE INVENTION
The present invention includes a nitride layer deposited over the field oxide region separating transistors in an array to reduce field leakage current. The nitride layer has a dense lattice, effectively blocking H+ and Na+ penetration from overlying layers into the field oxide. With ions such as H+ and Na+ not penetrating into the field oxide layer to cause the underlying p-substrate to become inverted and act like an n-type substrate, leakage current between source and drain regions of transistors separated by the field oxide layer is reduced. With such a nitride layer, transistors can be created with a desired threshold while maintaining a limited distance between source and drain regions of the transistor and a limited field oxide layer width.


REFERENCES:
patent: 4782037 (1988-11-01), Tomozawa et al.
patent: 5159353 (1992-10-01), Fasan et al.
patent: 5821153 (1998-10-01), Tsai et al.
patent: 5858830 (1999-01-01), Yoo et al.
patent: 5895243 (1999-04-01), Doan et al.
patent: 5908308 (1999-06-01), Barsan et al.
patent: 5939761 (1999-08-01), Dennison et al.
Stanley Wolf Silicon Processing for the VSLI Era vol. 2 Lattice Press p. 18, 1990.

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