Self-aligned contact structure and method

Details Self-aligned contact structure and method Self-aligned contact structure and method

1997-12-09

2001-04-10

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S659000

Reexamination Certificate

active

06214658

ABSTRACT:

TECHNICAL FIELD OF THE INVENTION
This invention relates in general to semiconductor fabrication, and more specifically to a self-aligned contact structure and method.
BACKGROUND OF THE INVENTION
Semiconductor device fabrication involves the forming of different components on a substrate using a variety of techniques, such as deposition, patterning, and etching. One component in semiconductor devices is a contact for coupling a layer of material to the underlying substrate or another layer. Depending on the particular application and the desired function, contacts may be holes, vias, channels or other geometric structures.
Efforts to miniaturize the components in a semiconductor device have begun to challenge the tolerance levels of the fabrication equipment. Several efforts attempt to further reduce the layout area of a semiconductor device using the same critical dimension dictated by the tolerances of the fabrication equipment. Existing techniques may offer some space savings by using traditional self-alignment techniques, but fail to accommodate a variety of different semiconductor devices and processes.
SUMMARY OF THE INVENTION
The disadvantages and problems associated with prior self-aligned contacts have been substantially reduced or eliminated by a self-aligned contact structure and method with enhanced flexibility and adaptability to accommodate a variety of fabrication techniques, such as complementary metal oxide semiconductor (CMOS) techniques.
In accordance with one embodiment of the present invention, a method is disclosed for forming a contact to a substrate, where the contact is disposed between two gates. The substrate between the gates is doped to form a source/drain region. A polysilicon layer overlying the source/drain region is formed. The polysilicon layer and the source/drain region are doped.
Technical advantages of the present invention include a self-aligned contact structure and method adapted to a variety of fabrication techniques, such as CMOS. Specifically, the self-aligned contact incorporates a non-doped polysilicon layer overlying the gates and the source/drain regions in a semiconductor device. The polysilicon layer may be doped as n-type, p-type, or other appropriate doping to support CMOS fabrication techniques and to offer enhanced flexibility and adaptability of the self-aligned contact. This structure greatly reduces alignment margin and increases the layout area of the semiconductor device using the same critical dimensions dictated by the fabrication equipment. Moreover, the polysilicon layer acts as a buffer during ion implantation, which reduces the depth of the source/drain region to improve peripheral isolation. Other technical advantages are apparent to one skilled in the art in view of the attached description, drawings, and claims.


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