Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-05-12
2001-07-24
Chaudhuri, Olik (Department: 2814)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S678000, C438S687000, C257S758000, C257S766000
Reexamination Certificate
active
06265301
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to methods used to create metal interconnect structures, and metal via structures, for semiconductor devices.
(2) Description of Prior Art
The semiconductor industry is continually striving to improve the performance of semiconductor devices, while still attempting to decrease the processing costs of semiconductor chips. These objectives have been successfully addressed via micro-miniaturization, or the ability to fabricate semiconductor devices, comprised with sub-micron features. The sub-micron features allow performance degrading capacitances to be reduced. In addition the use of sub-micron features, allow smaller semiconductor chips to be obtained, however still possessing the same, or greater, device densities, as counterparts fabricated using larger features. This results in the attainment of more semiconductor chips, from a specific size, starting substrate, thus reducing the processing cost of the sub-micron, semiconductor chip.
The success of micro-miniaturization can be attributed to advances in specific semiconductor fabrication disciplines such as photolithography and dry etching. The use of more sophisticated exposure cameras, as well as the use of more sensitive photoresist materials, have allowed sub-micron images in photoresist layers, to be routinely achieved. In addition the development of more advanced dry etching tools and processes, have allowed the sub-micron images, in masking photoresist layers, to be successfully transferred to underlying materials, used to fabricate semiconductor devices. However in addition to the contributions of advanced semiconductor disciplines, specific processing procedures, such as damascene, and dual damascene patterning, have been used to create, high aspect ratio, metal interconnect, and metal via structures, comprised with sub-micron features. However the damascene procedures, entailing forming the damascene, or dual damascene pattern, in. an insulator layer, followed by metal deposition, in the damascene opening, requires the use of “glue”, or adhesive layers, permanently located, underlying the metal structures, formed in the damascene opening. The “glue” or adhesive layer, now part of the metal structure, increases the resistance of the metal structure, for a specific cross-sectional area.
This invention will teach semiconductor procedures needed to create high aspect ratio, metal interconnect structures, and metal via structures, using electro-plating, or electro-less plating, metal procedures, thus avoiding the need for “glue” or adhesive layers, used with the conventional metal filling of damascene openings. The metal interconnect, and metal via structures, formed via use of this invention, will use a disposable conductive layer, or seed layer, thus not adversely influencing the conductivity of the resulting metal structure. Prior art, such as Brighton et al, in U.S. Pat. No. 4,866,008, describe the formation of metal structures, via electroplating procedures, however the final metal structures include the underlying seed layers, which adversely influence the ability to obtain the desired conductivity, for the metal structures.
SUMMARY OF THE INVENTION
It is object of this invention to fabricate metal interconnect structures, and metal via structures, via the opening of a desired metal structure shape, in a photoresist layer, followed by formation of the desired metal pattern, via a metal electroplating, or electro-less plating procedure, in the opening in the photoresist layer.
It is another object of this invention to deposit a disposable conductive layer, followed by formation of a defining, overlying shape, such as a photoresist, an organic, or a dielectric shape, exposing a portion of the disposable conductive layer, in the opening in the overlying shape.
It is still another object of this invention to electroplate, or electro-less plate, the desired metal pattern, in the opening in the photoresist shape, using the portion of disposable conductive layer, located under the defining shape, as a seed layer.
It is still yet another object of this invention to remove the portion of disposable conductive layer, not covered by the desired metal pattern, after removal of the overlying defining shape.
In accordance with the present invention a method of fabricating metal interconnect structures, and metal via structures, for semiconductor devices, using metal plating procedures, featuring underlying, disposable conductive layers, has been developed. A first disposable conductive layer is formed on an underlying, first metal via structure, followed by the formation of a first defining shape, comprised of an organic material, such as a photoresist, or comprised of a dielectric layer, featuring an opening, which exposes the top surface of the first metal via structure. A metal interconnect structure is formed on the portion of the first disposable conductive layer, exposed in the opening, in the first defining shape, via an electroplating, or electro-less plating procedure. After removal of the first defining shape, and removal of the portion of first disposable conductive layer, not covered by the metal interconnect structure, a dielectric layer is deposited, and planarized, exposing the top surface of the metal interconnect structure. After deposition of a second disposable conductive layer, overlying the exposed top surface of the metal interconnect structure, as well as overlying the planarized top surface of the dielectric layer, a second defining shape, comprised of either photoresist, other organic materials, or a dielectric, is formed, featuring an opening that exposes a region of the second disposable conductive layer, that directly overlays a portion of the top surface of the metal interconnect structure. A second metal via structure, or metal pillar structure, is formed on the portion of the second. disposable conductive layer, exposed in the opening in the second defining shape, via electroplating, or electro-less plating, procedures. After removal of the second defining shape, the portion of the second disposable conductive layer, not covered by the second metal via structure, is removed.
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Lee Jin-Yuan
Wang Chen-Jong
Ackerman Stephen B.
Chaudhuri Olik
Peralta Ginette
Saile George O.
Taiwan Semiconductor Manufacturing Company
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