Semiconductor device manufacturing method

Details Semiconductor device manufacturing method Semiconductor device manufacturing method

2000-08-14

2001-06-12

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S239000, C438S395000

Reexamination Certificate

active

06245621

ABSTRACT:

CROSS-REFERENCE TO RELATED APPLICATION
This application is related to Japanese application No. 2000-21327 filed on Jan. 31, 2000, whose priority is claimed under 35 USC §119, the disclosure of which is incorporated by reference in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and more specifically to a method for manufacturing a semiconductor device comprising a step of forming a contact hole extending from a gate electrode to a semiconductor substrate and/or device isolation region or a self-aligned contact hole to a semiconductor substrate between closely arranged gate electrodes.
2. Description of Related Art
With the advance of integration and performance of semiconductor devices, the design rule of its gate electrode has been also reduced to quarter micron or less and a source/drain region of a transistor has been narrowed, so that it has become difficult to form a contact hole.
Then, the following methods have been adopted in manufacturing a highly integrated semiconductor device, or SRAM in particular, by devising its layout. That is, a gate electrode is connected with a source/drain region of a transistor by one contact hole (shared contact hole), a contact hole extending from the source/drain region to the device isolation region (borderless contact hole), and/or a contact hole is formed on the source/drain region between closely arranged gate electrodes by means of SAC (self-aligned contact) method, for example.
In order to form the contact hole as described above, while the gate electrodes and the device isolation region which becomes the borderless section must be covered by a silicon nitride film which functions as an etching stopper in opening the contact hole by using the SAC method, a contact hole must be opened through the silicon nitride film on the gate electrode in the region where the shared contact hole is formed or the contact hole is formed on the gate electrode before etching the contact hole by SAC method.
As a method for opening the contact hole on the gate electrode covered by such silicon nitride film, there has been a method of forming a photoresist layer on the silicon nitride film by means of photolithography and of opening the contact hole by dry-etching by using the photoresist layer as a mask. It may be relatively easily carried out when the width of the gate electrode is wide and there is an enough margin of alignment.
However, when the width of the gate electrode is narrowed to accommodate with the high integration, it becomes difficult to align the mask in the photolithography and a part of a contact hole pattern of the photoresist layer extends over the source/drain region or the device isolation region.
When the dry-etching is carried out in this state, etching damage occurs on the semiconductor substrate in addition to etching-off of the silicon nitride film provided for the SAC method on the source/drain region. Etching-off of the silicon nitride film provided for the SAC method also occurs in the device isolation region. As a result, a large amount of etching loss of a silicon oxide film which is a device isolation film is produced during the SAC processing.
FIG.
11
(
a
) through FIG.
13
(
c
) show exemplary conventional semiconductor device manufacturing methods for opening a contact hole on a gate electrode covered by a silicon nitride film. FIG.
11
(
a
) to FIG.
11
(
c
) is a section view in which the contact hole is located only on source/drain regions
41
and
42
and FIGS.
12
(
a
) to
12
(
c
) and FIGS.
13
(
a
) to
13
(
b
) are section views in which the contact hole is located on the source/drain regions
41
and
42
and a device isolation region
32
. The reference numeral
41
denotes a high-concentrate source/drain regions and
42
a low-concentrate source/drain regions.
The device isolation region
32
is formed on a silicon substrate
31
. Then, a poly-crystal silicon film
34
, a tungsten silicide film
35
, an oxide film
36
and a silicon nitride film
37
are formed after forming a gate oxide film
33
and a gate electrode is formed by means of photolithography and dry-etching.
Then, the silicon nitride film is formed on the whole surface and etch-back is carried out to form a silicon nitride film sidewall
38
on the side of the gate electrode. A silicon nitride film
39
which becomes an etching stopper during the SAC method is formed on the whole surface (FIG.
11
(
a
) and FIG.
12
(
a
)).
After covering the gate electrode by the silicon nitride film, a resist mask
41
for opening the contact hole on the gate electrode is formed by means of photolithography. However, when the width of the gate electrode is narrow, it is difficult to register the mask by the lithography and a part of the contact hole pattern of the photoresist layer extends over the source/drain regions
41
and
42
or the device isolation region
32
(FIG.
11
(
b
) and FIG.
12
(
b
)).
When the dry-etching is carried in this state, the etching damages the semiconductor substrate
31
, in addition of etching-off of the silicon nitride film provided for the SAC processing, in the source/drain regions
41
and
42
(FIG.
11
(
c
) and FIG.
12
(
c
)).
Etching-off of the silicon nitride film provided for the SAC method occurs also in the device isolation region
32
. As a result, a large amount of etching loss of the oxide film which is the device isolation film occurs by the dry-etching using a SAC pattern photoresist layer
44
(FIG.
13
(
a
)) after forming an interlayer insulating film
43
(FIG.
13
(
b
)).
FIG.
13
(
c
) is a step section view after carrying out the SAC etching and removal of the photoresist.
Thus, when the misalignment of the mask occurs in the lithography in forming the contact hole on the gate electrode covered by the silicon nitride film, the part of the contact hole pattern of the photoresist extends over the source/drain regions or the device isolation region. Then, the source/drain regions are damaged by the etching, the etching-off of the silicon nitride film which becomes an etching stopper during the SAC method as well as the large amount of loss of the silicon oxide film during the SAC method thereafter have occurred, thus causing problems such as junction leak.
SUMMARY OF THE INVENTION
In view of the drawbacks of the prior art, the present invention provides a method for manufacturing a semiconductor device having an etching stopper which causes no damage in the source/drain regions even if the misalignment of the mask occurs in the lithography and no etching-off of the silicon nitride film which becomes the etching stopper during the SAC method in the borderless device isolation region in creating the contact hole on the gate electrode covered by the silicon nitride film.
In other words, the present invention provides a method for manufacturing a semiconductor device, comprising steps of:
(a) forming a gate insulating film on a semiconductor substrate and forming a plurality of gate electrodes having a first insulating film made of a first insulating material thereon and a sidewall spacer made of the first insulating material on its sidewall on said gate insulating film;
(b) forming a second insulating film which is made of the first insulating material and which is thinner than said first insulating film on said semiconductor substrate at least in a region where a contact hole is to be formed in the later step;
(c) embedding a third insulating film which may become an etching stopper to etching of said first insulating material between said gate electrodes;
(d) forming a first resist pattern having a predetermined shape on said semiconductor substrate and etching said second insulating film, first insulating film and sidewall spacer until when said gate electrode is exposed by using said first resist pattern and said third insulating film as mask;
(e) forming an interlayer insulating film on said semiconductor substrate;
(f) forming a second resist pattern having a predetermined shape on said interl

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