Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-17
2001-04-24
Wilczewski, Mary (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S261000, C438S262000, C438S263000, C438S265000
Reexamination Certificate
active
06221718
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 87113258, filed Aug. 12, 1998, the full disclosure of which is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor fabrication technology, and more particularly, to a method of fabricating a flash memory with buried bit lines.
2. Description of Related Art
Flash memory is a type of erasable and programmable read-only memory (EPROM) that can be easily and quickly reprogrammed. In a flash memory device, each memory cell is formed with a two-layer gate structure (called stacked gate) including a floating gate and a control gate. The floating gate is typically formed from polysilicon and is so named because it is not physically connected to any other conductive structures in the integrated circuit. Whether or not data is stored on a memory cell is dependent on whether or not the floating gate of the memory cell is charged. The control gate is formed over the floating gate and connected to a word line to control the access to the memory cell.
FIG. 1
is a schematic diagram showing the circuit layout of an array of flash memory cells (one of which is enclosed in a dashed circle indicated by the reference numeral
10
). These flash memory cells can be accessed via a plurality of word lines WL
1
, WL
2
and a plurality of bit lines BL
1
, BL
2
, BL
3
that are interconnected in a pre-determined manner to the flash memory device. The access operation for each flash memory cell (i.e., read/write operation) is performed a phenomenon called Fowler-Nordheim tunneling (F-N tunneling) between the floating gates and the associated impurity-doped regions. The access speed is dependent on the mobility of electrons between the floating gates and the impurity-doped regions. The access operation is basic knowledge to those skilled in the art of semiconductor memory devices, so description thereof will not be further detailed.
It is a trend in semiconductor industry to fabricate integrated circuits with high integration. To meet this requirement, the present layout design for the flash memory should be miniaturized in size. However, the achievable level of miniaturization is limited by the present design rule. The fabrication of buried bit lines in a miniaturized, conventional flash memory device would be complex and thus difficult to carry out.
SUMMARY OF THE INVENTION
It is therefore an objective of the present invention to provide a flash memory with buried bit lines that are lower in resistance and shallower in buried depth in the substrate than the prior art due to the forming of shallow N
+
junctions.
It is another objective of the present invention to provide a flash memory structure with buried bit lines that are formed with a shallow N
+
junction having a smaller contact area with the substrate so that the punchthrough margin can be increased to allow enhanced reliability to the flash memory device.
In accordance with the foregoing and other objectives of the present invention, a method of fabricating a flash memory is provided.
The method according to the invention to fabricate the foregoing a flash memory structure includes the following steps of: preparing a semiconductor substrate; then forming a tunneling oxide layer over the substrate; then, forming a first conductive layer over the tunneling oxide layer; next, forming a layer of silicon nitride over the first conductive layer; then, performing a photolithographic and etching process to etch away selected portions of the silicon nitride layer and the underlying first conductive layer until the surface of the tunneling oxide layer is exposed, with the remaining portions of the first conductive layer serving as a plurality of floating gates; subsequently, forming a plurality of sidewall spacers, each on the sidewall of one stacked structure of one floating gate and the overlying silicon nitride layer; then, with the sidewall spacers serving as mask, removing the unmasked portions of the tunneling oxide layer until the surface of the substrate is exposed; then, forming a plurality of selective polysilicon blocks, each between one neighboring pair of the floating gates; then, with the silicon nitride layers and the sidewall spacers serving as mask, performing an ion-implantation process to dope an impurity element through the selective polysilicon blocks into the substrate to form a plurality of impurity-doped regions serving as buried bit line in the substrate; next, forming an insulating layer over the selective polysilicon blocks to a thickness above the silicon nitride layers over the floating gates; next, removing an upper part of the insulating layer above the silicon nitride layer, with the remaining part of the same being left over the selective polysilicon blocks; next, removing the silicon nitride layer over each of the floating gates; then, forming a dielectric layer covering each of floating gates and the insulating layer; next, forming a second conductive layer over the dielectric layer; and finally, performing a selective removal process on the second conductive layer in such a manner that the remaining portions thereof serve as control gates over the floating gates.
REFERENCES:
patent: 4980739 (1990-12-01), Favreau
patent: 5536668 (1996-07-01), An et al.
patent: 5572056 (1996-11-01), Hsue et al.
patent: 5635415 (1997-06-01), Hong
patent: 5811337 (1998-09-01), Wen
patent: 6008087 (1999-12-01), Wu
Huang Jiawei
J.C. Patents
United Microelectronics Corp.
Wilczewski Mary
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