Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-29
2001-08-14
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S770000, C438S971000
Reexamination Certificate
active
06274429
ABSTRACT:
FIELD OF THE INVENTION
The invention is generally related to the field of semiconductor processing and more specifically to the use of a Si-rich oxide barrier.
BACKGROUND OF THE INVENTION
It is known that the manufacturing of semiconductor devices comprises a chemical processing consisting of a series of steps in which different elements of the devices to be manufactured are progressively made. The semiconductor mainly used is silicon.
Frequently, for silicon devices, one or more steps are required during said chemical processing in which a silicon dioxide should be obtained.
This requirement is particularly demanding in manufacturing electrically programmable fast access non volatile memories, so-called “Flash EPROM”, that are provided with Floating-Gate-Avalanche-Injection MOS transistors, called “FAMOS”, substantially made up of MOS transistors the gate regions of which are insulated.
Preferably, said FAMOS transistors include, upon the channel area of the substrate, a structure made up of a stack of different layers, so called gate stack, comprising, starting from the surface in contact with the silicon substrate:
an electrically conductive layer, called Poly1, of polycrystalline silicon known as polysilicon, in contact with the substrate;
an electrically insulating, three layer structure (oxide—nitride—oxide) of silicon (SiO
2
—Si
3
N
4
—SiO
2
), known as “ONO”;
an electrically conductive layer, called Poly2, of polysilicon, forming the floating gate region; and
an electrically conductive metallic layer of tungsten silicide with variable composition (WSi
x
), in contact with the Poly2 layer.
For the purpose of obtaining a good adhesion between the silicide and Poly2 layers, an annealing step in oxygen atmosphere is performed upon ending manufacturing said gate stack, so as to promote the growth of a thin layer of silicon dioxide on the silicide and on the substrate exposed to gas. The subsequent steps of device chemical treatment separately carry out the doping of the source and drain regions of FAMOS transistors, and, finally, the metallization and passivation of the manufactured devices.
The quality of a Flash EPROM memory is established by quantifying one or more specifically defined parameters. In particular, an important parameter for evaluating the quality of a Flash EPROM memory is the “data retention loss”, known as DRL. Said DRL is quantified by testing the capability of the memory device in retaining test data when it is subjected to severely stressing treatments, such as, for example, high temperature treatments. The comparison between the charges stored in the memory device before and after such a treatment provides a measure of the device DRL. A low value of DRL indicates a long lifetime for the stored charge and, therefore, a better quality of the Flash EPROM memory device.
To minimize the DRL of Flash EPROM devices, the presence of an oxide layer is required in order to protect said gate stacks.
The silicon dioxide layer, that is grown on the device with the aforementioned annealing step carried out to obtain a better adhersion between silicide and Poly2, is not sufficient and it is removed by the subsequent chemical treatment or “etching” preliminary to dopant implantations on the source regions of the FAMOS transistors during the Self Aligned Source (SAS) etch process. The SAS plasma etch process is known to remove the protective thermal oxide layer from the source regions of the FAMOS transistors.
Hence, aiming at minimizing the DRL, a new oxidation step is required. In Prior Art this implies a new annealing step under oxygen atmosphere, i.e. a new thermal oxidation.
However, executing a new thermal oxidation has some drawbacks.
First of all, the oxidation does not uniformly occur on the various layers of the gate stack, thereby causing the so-called peeling of the silicide layer and a reciprocal lifting between layers.
Moreover, when the thermal oxidation step is executed after performing dopant implantations, the dopants diffuse very fast in the substrate crystal lattice till they concentrate, thereby producing dislocations and defects and causing short circuits between the source and drain regions.
Therefore, performing a new thermal oxidation involves severe reliability problems, with resulting degradation of the device quality to a lower level as the one obtainable without a protection oxide layer.
In conclusion, the oxidation according to the prior art to minimize DRL is not feasible due to the high agressiveness of the thermal oxidation.
Consequently, DRL is not effectively minimizable and this implies significant economical losses, because 5% of manufactured devices are not reliable and have to be scrapped.
SUMMARY OF THE INVENTION
The invention is an oxidation process comprising the steps of (1) low temperature deposition of a silicon-enriched silicon oxide over a semiconductor structure and (2) annealing said silicon-enriched oxide at a high temperature in an oxygen atmosphere to convert said silicon-enriched oxide to a thermal oxide.
An advantage of the invention is providing an oxidation process that can reduce the DRL when used in a process for forming a FAMOS transistor.
Another advantage of the invention is providing a less aggressive oxidation process that results in a thermal oxide without the drawbacks of a conventional thermal oxidation process.
Another advantage of the invention is providing an oxidation process having reduced impact on oxidation induced defects within the substrate.
These and other advantages will be apparent to those of ordinary skill in the art having reference to the specification in conjunction with the drawings.
REFERENCES:
patent: 5290727 (1994-03-01), Jain et al.
patent: 5602056 (1997-02-01), Jain et al.
patent: 5726070 (1998-03-01), Hong et al.
patent: 5731242 (1998-03-01), Parat et al.
Booth Richard
Brady III W. James
Garner Jacqueline J.
Telecky , Jr. Frederick J.
Texas Instruments Incorporated
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