Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-03
2001-05-08
Tsai, Jey (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000
Reexamination Certificate
active
06228700
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing dynamic random access memory (DRAM). More particularly, the present invention relates to a method for manufacturing a capacitor over bit line (COB) type of DRAM.
2. Description of the Related Art
DRAM is an important electronic component in the data communications industry. Advances in semiconductor processing techniques have yielded high-capacity DRAMs that occupy only a very small volume. Currently, the capacitor over bit line (COB) type of DRAM is widely adopted.
FIGS. 1A and 1B
are schematic views showing the steps in producing a conventional COB type of DRAM.
As shown in
FIG. 1A
, a substrate
100
is provided. Shallow trench isolation (STI) structures
102
are formed in the substrate
100
so that an active region
104
is marked out. A word line structure
112
is formed by depositing a gate oxide layer
106
, a gate electrode
108
and a cap layer
110
in sequence. Substrate regions having a lightly doped drain structures
114
are formed on each side of the word line structure
112
. Spacers
116
are formed on the sidewalls of the word line structure
112
. Source/drain terminals
118
are formed in the substrate
100
. Dielectric material is deposited over the substrate
100
to form a first dielectric layer
120
. A portion of the first dielectric layer
120
is removed to form a bit line contact opening
122
that exposes a source terminal
118
.
As shown in
FIG. 1B
, a bit line structure
124
is formed over the first dielectric layer
120
. The bit line structure
124
is electrically connected to the source terminal
118
via the bit line contact
122
. Dielectric material is again deposited over the substrate
100
to form a second dielectric layer
126
. A node contact opening
128
that passes through the second dielectric layer
126
and the first dielectric layer
120
and exposes the drain terminal
118
is formed. A node contact
130
is formed inside the node contact opening
128
so that the drain terminal is electrically linked. A capacitor structure
132
is formed above the second dielectric layer
126
. The capacitor structure
132
is electrically connected to the drain terminal via the node contact
130
. Since the node contact
130
and the bit line structure
124
are formed in different cross-sectional planes, dashed lines are used to outline the positions of the node contact opening
128
and the node contact
130
in FIG.
1
B.
In the aforementioned method of forming COB type capacitor, the bit line contact opening in the first dielectric layer may be slightly misaligned. Therefore, a tighter design rule is often adopted for the bit line contact in order to prevent poor electrical connection or failure of the bit line contact to connect with the source terminal.
In addition, the first and the second dielectric layer have to be etched when the node electrode opening is formed. Because a thick layer of dielectric material needs to be removed, the etching process is harder. Furthermore, the aspect ratio of the node contact opening is relatively large. Hence, forming a node contact inside the node contact opening is a difficult process. Moreover, some voids are likely to form within the node contact, leading to a considerable increase in resistance between the node contact and the drain terminal.
SUMMARY OF THE INVENTION
Accordingly, one object of the present invention is to provide a method for manufacturing DRAM having fewer difficult processing steps and more relaxed design rules.
A second object of this invention is to provide a method for manufacturing a COB type of DRAM such that the aspect ratio of a node contact opening needed to accommodate a node contact that leads to a capacitor is effectively reduced. Hence, quality of the node contact is improved.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method for manufacturing DRAM. Shallow trench isolation (STI) structures are formed in a substrate marking out active regions, wherein width and length of the active region is controlled by the STI structures. A gate oxide layer, a conductive layer and a barrier layer are sequentially formed over the substrate. Using photolithographic and etching techniques, a portion of the conductive layer and the barrier layer are removed to form bit line contact openings and node contact openings. The bit line contact openings and the node contact openings expose a portion of the gate oxide layer in the active region and a portion of the gate oxide layer above the STI structure. The operation also marks out an area above the active region for accommodating a word line. However, neighboring word line structures are still joined together by a portion of the conductive layer and barrier layer. A lightly doped drain structure is formed in the substrate exposed by the bit line contact openings and the node contact openings. Spacers are formed on the sidewalls of the bit line contact openings and the node contact openings. The exposed gate oxide layer at the bottom of the bit line contact openings and the node contact openings are removed so that a portion of the substrate is exposed. Source terminals are formed in the substrate regions exposed by the bit line contact openings while drain terminals are formed in the substrate regions exposed by the node contact openings.
In the subsequent step, a bit line plug is formed in each bit line contact opening while a landing pad is formed in each node contact opening. Since each bit line contact opening and each node contact opening cover a portion of the active region and a portion at the top of the STI structure, area at the top of the bit line plug is larger than the source terminal while area at the top of the landing pad is larger than the drain terminal. An oxide layer is formed over the bit line plug and the landing pad. Using photolithographic and etching techniques, word line patterning is carried out to remove the conductive layer and barrier layer between neighboring word lines. Because a portion of the barrier layer and conductive layer has to be removed in the word line patterning operation, a high etching selectivity of oxide relative to the material forming the barrier layer and the conductive layer makes the oxide layer above the bit line plug and the landing pad an effective protection against possible damages due to etching. A first dielectric layer is formed over the substrate. First contact openings are formed in the first dielectric layer to expose the bit line plugs. Since the first dielectric layer is made from an oxide material, a portion of the oxide layer is removed when the first contact opening is formed. A bit line structure is formed over the first dielectric layer. The bit line structure is electrically connected to the bit line plug via the first contact.
A second dielectric layer is formed over the substrate. A second contact opening that passes through the second dielectric layer and the first dielectric layer is formed. A second node contact is formed inside the second contact opening, and then a capacitor is formed over the second dielectric layer. The capacitor is electrically connected to the second node contact, while the second node contact is electrically connected to the landing pad.
In a second embodiment of this invention, a landing pad contact opening that exposes the landing pad contact is formed in the first dielectric layer together with the first contact opening that exposes a portion of the bit line plug. When the bit line structure is formed over the first dielectric layer, a second landing pad is formed inside the landing pad contact opening. In the subsequent step, a second dielectric layer is formed over the substrate, and then a second contact opening that exposes the second landing pad is formed in the second dielectric layer. A second node contact is formed inside the second contact opening. Finally, a capacitor is formed over the secon
Thomas Kayden Horstemeyer & Risley
Tsai Jey
United Microelectronics Corp.
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