Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-09-27
2001-09-25
Quach, T. N. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S533000, C438S586000, C438S664000
Reexamination Certificate
active
06294434
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a method used to form a metal silicide layer on a polysilicon gate structure, as well as on a source/drain region of a metal oxide semiconductor field effect transistor, (MOSFET), device.
(2) Description of Prior Art
Increased device performance is a major objective of the semiconductor industry. The ability to decrease resistance-capacitance (RC), delays allows the desired performance increases to be realized. The advent of micro-miniaturization, or the ability to fabricate semiconductor devices with sub-micron features, have resulted in decreased junction capacitance, thus increased device performance as a result of the use of smaller dimension diffused regions. In addition the resistance component of the RC delay factor has in part been addressed via resistance decreases in word line and bit line resistance, via the use of metal silicide layers formed on both gate structures as well as on source/drain regions. One method of forming metal silicide layers on these regions has been the use of a Self-ALIgned metal siliCIDE, (salicide), procedure, in which a blanket metal is deposited, annealed to form the desired metal silicide layer on regions in which the metal layer overlaid silicon, (top surface of gate structure and source/drain region), followed by the removal of unreacted metal from insulator surfaces, such as insulator spacers located on the sides of the gate structure. However one problem encountered with the salicide procedure is the inability to completely remove unreacted metal from the insulator spacers, resulting in gate to substrate leakage or shorts. In addition prolonged anneal cycles, used to insure salicide reaction can result in the formation of metal silicide ribbons on the surface of the insulator spacers, extending from the gate structure to source/drain regions, again resulting in yield loss in terms of gate to substrate leakage or shorts.
The present invention will describe a procedure for forming metal silicide on a polysilicon gate structure, as well as on a source/drain region, however using implantation of metal ions only into the top surface of the polysilicon gate structure and into the top surface of a source/drain region. This feature, selectively placing metal only in regions in which the metal silicide layer is desired, eliminates the risk of forming ribbons, or leaving unreacted metal, on the sides of the insulator spacers, sometimes encountered with the salicide procedure employing vacuum deposition of a blanket metal layer, used for subsequent salicide formation. Prior art, such as Fazan et al, in U.S. Pat. No. 6,087,700, describe a method of forming a metal silicide layer on a blanket polysilicon layer, prior to defining the metal silicide-polysilicon gate structure. That prior art however does not describe this present invention in which metal silicide is formed on the top surface of a defined polysilicon gate structure, and on a source/drain region, via implantation of metal ions.
SUMMARY OF THE INVENTION
It is an object of this invention to form a metal silicide layer only on a polysilicon gate structure and on a source/drain region of a MOSFET device.
It is another object of this invention to implant metal ions into a top portion of a defined polysilicon gate structure, and into a top portion of a source/drain region of a MOSFET device.
It is yet another object of this invention to perform an anneal cycle to form metal silicide on the source/drain region, and to form a metal silicide layer on the defined polysilicon structure, via reaction of the implanted metal ions and silicon, available from the polysilicon gate structure and from the source/drain region.
It is still yet another object of this invention to selectively remove unreacted metal ions from the surface of the metal silicide layer.
In accordance with the present invention a method of forming a metal silicide layer for a salicide gate structure, and forming a metal silicide layer on a source/drain region of a MOSFET device, featuring a metal implantation procedure used to supply the metal component of the metal silicide layer, is described. A polysilicon gate structure is formed on the an underlying silicon dioxide gate insulator layer, followed by formation of insulator spacers on the sides of the polysilicon gate structure. A heavily doped source/drain region is formed in a region of the semiconductor substrate not covered by the polysilicon gate structure or by the insulator spacers. Metal ions are next implanted into a top portion of the defined polysilicon gate structure, as well as into a top portion of the heavily doped source/drain region. A first anneal procedure is then used to form the desired metal silicide layer on the top surface of the heavily doped source/drain region, as well as on the top surface of the polysilicon gate structure, creating a salicide gate structure. Unreacted metal ions are then selectively removed from the top surface of the metal silicide layers. An optional second anneal cycle can next be performed to create a lower resistance phase of the metal silicide layers.
REFERENCES:
patent: 5563100 (1996-10-01), Matsubara
patent: 5858846 (1999-01-01), Tsai et al.
patent: 5918141 (1999-06-01), Merrill
patent: 6087700 (2000-07-01), Fazan et al.
patent: 0455284-A1 (1991-11-01), None
Ackerman Stephen B.
Quach T. N.
Saile George O.
Vanguard International Semiconductor Corporation
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