Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-11-01
2001-06-26
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S763000
Reexamination Certificate
active
06251724
ABSTRACT:
BACKGROUND OF INVENTION
1. Field of the Invention
This invention relates generally to fabrication of capacitors for semiconductor devices and more particularly to the fabrication of a capacitors and pad contacts for an analog integrated circuit device.
2. Description of the Prior Art
In the fabrication of combined analog and digital integrated circuits it is common to form capacitors over field oxide regions and form MOS FET near by. For the inventors to improve the capacitor performance, higher dielectric constant capacitor SiN (silicon nitride) is deposited over the bottom storage electrode (poly-1) layer and before the interlevel dielectric (ILD).
The inventors have found that the SiN over the polysilicon bottom plate causes Threshold voltage (Vt) uniformity problems.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering U.S. Pat. No. 5,658,821 (Chen et al.) Method of improving uniformity of metal-to-poly capacitors composed by polysilicon oxide and avoiding device damage—that discloses a method for the formation of capacitors comprising a polysilicon first capacitor plate, polysilicon oxide dielectric, and a metal second capacitor plate which improves uniformity of capacitance and avoids device damage. More particularly the patent discloses conditioning the polysilicon first capacitor plate by forming a thin layer of polysilicon oxide on the polysilicon followed by removal of the polysilicon oxide using a buffered oxide etch or a dry anisotropic etch. A first layer of polysilicon oxide is formed on a polysilicon first capacitor plate. The wafer is then dipped in a buffered oxide etch or subjected to a dry anisotropic etch. The etching conditions the polysilicon layer so that subsequent polysilicon oxide growth is very uniform and controllable. A second polysilicon oxide layer is then formed on the polysilicon first capacitor plate. A layer of silicon nitride is formed on the polysilicon oxide and a second capacitor plate is formed on the layer of silicon nitride completing the capacitor. Improved capacitance uniformity across the wafer is achieved and device damage is avoided.
U.S. Pat. No. 4,922,312 (Coleman et al.) DRAM process with improved polysilicon-to-polysilicon capacitor and the capacitor and U.S. Pat. No. 5,098,192 (Colemen et al.) and U.S. Pat. No. 5,244,825(U.S. Pat. No. 5,098,192 (Colemen et al.)—teach methods for fabrication of DRAM cells having an upper capacitor plate over the polysilicon storage gate. To provide a very high specific capacitance and very good integrity between the first polysilicon storage gate and the (second or third polysilicon) upper capacitor plate, the dielectric is formed as an oxide
itride composite which is then reoxidized. This provides the advantages of high dielectric integrity, high specific capacitance, uniformity and reproducibility.
However, further improvements can be made to improve the VT uniformity.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for fabricating a analog capacitor which has more uniform VT.
It is an object of the present invention to provide a method for fabricating a pad contact and a capacitor where the SiN over the poly-1 in the pad contact is removed to make She VT more uniform.
It is an object of the present invention to provide a method for fabricating a scribe area and a capacitor where the SiN over the poly-1 in the scribe area is removed to make the VT more uniform.
It is an object of the present invention to provide a method for fabricating a process control monitor (PCM) testsite and a capacitor where the SiN over the poly-1 in the process control monitor (PCM) is removed to make the VT more uniform.
To accomplish the above objectives, the present invention provides a method of manufacturing a capacitor for an analog IC which is characterized as follows.
In a first embodiment of the invention, the silicon nitride capacitor dielectric layer
28
is etched away from over the poly-1 layer
18
C in the pad area
8
. The removal of the SiN layer
18
C allows H
2
to penetrate into the poly-1 layer
18
C and improve the VT.
The inventors have found that threshold voltage (Vt or VT) uniformity is improved when the clear out ratio (area of SiN removed/total area of SiN on whole wafer) is between 1.0584% and 99% and more preferably greater than 1.06%. Uniformity of long channel VT-N was improved when we modify the pad structure of PCM to increase the clear out ratio of capacitor Si
3
N
4
to 1.0584%.
In a second embodiment of the invention, the silicon nitride capacitor dielectric is etched away from over the poly-1 layer
18
C in the pad areas
137
in the process control monitor (PCM) testsite areas
135
between the chips
100
.
In a third embodiment of the invention, the silicon nitride capacitor dielectric is etched away from over the poly-1 layer
18
C in the scribe area
130
131
between the between the chips
100
.
The invention can comprise: providing a substrate having devices formed therein; the substrate having device areas and pad areas We providing field oxide isolation regions in the silicon substrate. providing contact regions on the substrate. forming a first polysilicon layer over the substrate. Then the first polysilicon layer is patterned to define first polysilicon capacitor plates on the field oxide isolation regions. and gate electrodes over the substrate. and polysilicon pads over the pad area.
We form a IPO layer of insulator dielectric over the substrate covering the first polysilicon capacitor plates and gate electrodes and polysilicon pads. Next, a silicon nitride layer is formed over the PO layer and an ELD layer is formed over the silicon nitride layer. Next, a contact etch is performed by patterning the ILD layer to define a contact opening exposing the contact region in the device area.
We then perform a capacitor/pad opening etch by etching the ILD layer to form a capacitor opening over the first polysilicon capacitor plates and to form a pad opening over the pad area. Next, in a key step we perform a pad etch to remove the nitride layer and the IPO layer over the polysilicon pads in the pad areas.
In a preferred embodiment the invention further includes forming top polysilicon plate over the first polysilicon capacitor plates, and forming a Pad metal in the pad area.
In a preferred embodiment the invention the pad area is within a testsite area in a scribe area between chip areas.
In a preferred embodiment the invention the pad area is within a testsite pad area. In a preferred embodiment the invention the pad area is within a chip area in the device area.
In a preferred embodiment the invention further includes: the substrate having scribe areas between the device areas. the device areas are chip areas. The capacitor/pad opening etch removes the ILD layer from over the scribe areas. the pad etch to remove the nitride layer and the IPO layer over the scribe areas.
Additional objects and advantages of the invention will be set forth in the description that follows, and in part will be obvious from the description, or may be learned by practice of the invention. The objects and advantages of the invention may be realized and obtained by means of instrumentalities and combinations particularly pointed out in the append claims.
REFERENCES:
patent: 4922312 (1990-05-01), Coleman et al.
patent: 5098192 (1992-03-01), Coleman et al.
patent: 5244825 (1993-09-01), Coleman et al.
patent: 5624864 (1997-04-01), Arita et al.
patent: 5658821 (1997-08-01), Chen et al.
patent: 5913121 (1999-06-01), Kasai
Ku Shu-Mei
Wu Lin-June
Ackerman Stephen B.
Chaudhari Chandra
Saile George O.
Stoffel William J.
Taiwan Semiconductor Manufacturing Company
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