Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-02-05
2001-07-10
Thomas, Tom (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S218000, C438S220000, C438S221000, C438S223000, C438S224000, C438S227000, C438S228000, C438S237000, C257S372000, C257S371000, C257S351000, C257S352000, C257S354000
Reexamination Certificate
active
06258641
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to methods of producing integrated circuits on a semiconductor wafer, and more particularly to methods of fabricating complementary metal oxide semiconductor (CMOS) transistors without causing latchup.
2. Description of the Related Art
Latchup is a phenomenon of CMOS circuits and is well described by S. Wolf in
Silicon Processing for the VLSI Era,
Volume 2, by Lattice Press, copyright 1990, 6.4 LATCHUP IN CMOS, page 400: “A major problem in CMOS circuits is the inherent, self-destructive phenomenon known as latchup. Latchup is a phenomenon that establishes a very low-resistance path between the V
DD
and V
SS
power lines, allowing large currents to flow through the circuit. This can cause the circuit to cease functioning or even to destroy itself (due to heat damage caused by high power dissipation).
The susceptibility to latchup arises from the presence of complementary parasitic bipolar transistor structures, which result from the fabrication of the complementary MOS devices in CMOS structures. Since they are in close proximity to one another, the complementary bipolar structures can interact electrically to form device structures which behave like pnpn diodes.”
FIG. 1
shows a cross-sectional view of a p-well CMOS inverter with input V
in
, output V
out
, supply voltage (+)V
dd
, and reference voltage (−)V
ss
. The n-channel (NMOS) transistor is in the p-well. Q
1
is the lateral pnp parasitic transistor structure and Q
2
is the vertical npn parasitic transistor structure which results from the arrangement of NMOS and p-channel (PMOS) transistors. The lateral transistor Q
1
comprises the source S of the PMOS transistor (emitter), the n-substrate (base), and the p-well (collector). The vertical transistor Q
2
comprises the source S of the NMOS transistor (emitter), the p-well (base), and the n-substrate (collector). The region of each terminal is identified by a circle with an “n” or a “p”. Substrate current flows from (+)V
dd
through the n-substrate, having a resistance R
sub
, to the collector of Q
2
. P-well current flows from the collector of Q
1
through the p-well, having resistance R
p-well
, to (−)V
ss
.
FIG. 2
, is an equivalent circuit diagram of the parasitic transistors of FIG.
1
. Again the region of each transistor terminal is identified by a circle with an “n” or a “p”. In this circuit the base of each transistor is connected to the collector of the other transistor. Inspection of
FIG. 2
shows that this circuit is the equivalent of a parasitic pnpn diode (from emitter of Q
1
to emitter of Q
2
). A pnpn diode below a certain “trigger” voltage acts as a high impedance, but when biased beyond that “trigger” voltage will act as a low impedance device similar to a forward biased diode. This results in a current that depends on R
sub
and R
p-well
and can be destructive to the CMOS circuit.
Clearly, latchup is not a new problem, however, it is becoming much more severe as devices shrink to quarter and sub-quarter micron dimensions, because of the reduced well depth and inter-well spacing. The method of providing a guard ring only stabilizes the potential on the surface and, hence, is not efficient in preventing latchup in the bulk of the semiconductor. Latchup can be avoided by isolating n-wells from p-wells at the cost of consuming more silicon real estate. Quoting from S. Wolf in
Silicon Processing for the VLSI Era,
Volume 3, by Lattice Press, copyright 1995, 6.6 CMOS ISOLATION TECHNOLOGY, page 374:
“The large area penalty of p-channel-to-n-channel device isolation is the most important reason why CMOS technologies using conventional isolation methods cannot achieve as high a packing density as NMOS. Furthermore, while new techniques such as epitaxy greatly reduce latchup susceptibility as CMOS is scaled down, they generally do not suppress leakage currents in the parasitic MOS structures. Hence, the layout spacing between an n-channel and a p-channel device may be limited by isolation failure rather than by latchup.”
A large number of workers in the field have tackled the problem and found solutions which are suitable to one application or another, but the problem of latchup keeps on surfacing as transistor dimensions decrease in both the horizontal and vertical dimension.
U.S. Pat. No. 5,397,734 (Iguchi et al.) shows a method for fabrication a triple well construction.
U.S. Pat. No. 5,453,397 (Ema et al.) discloses a method capable of isolating fine pattern elements using LOCOS.
U.S. Pat. No. 5,470,766 (Lien) teaches a triple well with a p-region under FOX isolation regions. Lien addresses latch-up immunity for PMOS FETs.
U.S. Pat. No. 5,595,925 (Chen et al.) describes another triple well structure.
U.S. Pat. No. 5,604,150 (Mehrad) discloses a triple-well structure, where the channel-stop impurity is implanted using multiple doses at different energies.
U.S. Pat. No. 5,702,988 (Liang) teaches a method of forming a triple-well structure having n-well, p-well, and p-well in n-well regions.
None of the above-cited examples of the related art provide the combination of shallow trench isolation (STI) structures with a buried p-well, tieing the buried p-well to ground, and the deep n-well to Vdd to prevent latchup in deep sub-quarter micron technology.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide methods to prevent the inherent latchup problem of CMOS circuits by eliminating the low resistance between the Vdd and Vss power rails caused by the latchup of parasitic, complementary bipolar transistors which are present in CMOS devices.
Another object of the present invention is to eliminate the use of guard rings and their concomitant penalty in silicon real estate.
A further object of the present invention is to provide the above benefits without adding additional masks or processes.
A yet further object of the present invention is to provide the above benefits for sub-quarter micron transistors.
These objects have been achieved by using a deep n-well to disconnect the pnp collector to npn base connection of two parasitic bipolar transistors, and by using a buried p-well to disconnect the npn collector to pnp base connection of those same two parasitic transistors. Furthermore, the deep n-well is shorted to a supply voltage V
dd
, and the buried p-well is shorted to a reference voltage V
ss
via both the P substrate and a P
+
ground tab.
REFERENCES:
patent: 5397734 (1995-03-01), Iguchi et al.
patent: 5453397 (1995-09-01), Ema et al.
patent: 5470766 (1995-11-01), Lien
patent: 5595925 (1997-01-01), Chen et al.
patent: 5604150 (1997-02-01), Mehrad
patent: 5702988 (1997-12-01), Liang
Wolf, “Silicon Processing for the VLSI Era”, vol. 2: Process Integration, Lattice Press, Sunset Beach, CA (1990), p. 410.
Wolf, “Silicon Processing for the VLSI Era”, vol. 3: The Submicron MOSFET, Lattice Press, Sunset Beach, CA (1995), p. 374.
Liang Mong-Song
Wong Shyh Chyi
Ackerman Stephen B.
Saile George O.
Souw Bernard E.
Taiwan Semiconductor Manufacturing Company
Thomas Tom
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