Error detection/correction and fault detection/recovery – Pulse or data error handling – Digital logic testing
Reexamination Certificate
1994-09-06
2001-04-17
Beausoliel, Jr., Robert W. (Department: 2184)
Error detection/correction and fault detection/recovery
Pulse or data error handling
Digital logic testing
C714S030000
Reexamination Certificate
active
06219811
ABSTRACT:
FIELD OF THE INVENTION
The invention relates to a circuit, system, and method which provides interconnect test capability for chips that have a transceiver circuit and storage circuit.
BACKGROUND OF THE INVENTION
One of the best known test methods for testing large scale integrated circuits is level sensitive scan design (LSSD) which is described in the article “A Logic Design Structure for LSI Testability”, Proceedings of the Design Automation Conference, No. 14, 20-22, June 1977, New Orleans, La., by E. B. Eichelberger. See also U.S. Pat. No. 4,590,078, U.S. Pat. No. 4,428,060 and E. J. McCluskey, “A Survey of Design for Test-ability Scan Techniques”, VLSI Design, Dec. 1984, pp. 38-61, for a comprehensive list of patents and publications for the testing of electronic structures.
Cordt W. Starke, “Design for Testability and Diagnosis in a VLSI CMOS System/370 Processor”, IBM Journal of Research and Development, Volume 34, No. 2/3, March/May 1990, pp. 355-362, describes a design of combinational logic circuits which incorporates on-chip test pattern generation and on-chip test response evaluation for logic fault detection. In this paper, the combinational logic circuits are coupled together in a typical level-sensitive scan design (LSSD) by shift register latches (SRL's) which are configured to form a test scan path. The test patterns are generated by a linear feed back shift register (LFSR) which is configured as a pseudo-random pattern generator which is implemented on the chip. To apply a test pattern, the shift register latches are loaded via the test scan path. Then the system clocks are pulsed once to execute one operational cycle of the system. After the system clocks are applied, the test response is shifted out of the shift register latches via the test scan path for further evaluation. However, the above cited prior art is silent as to interconnect testing of chips and only refers to the internal testing of a chip.
IEEE Standard 1149.11 and C. M. Maunder, R. E. Tulloss, “The Test Access Port and Boundary-Scan Architecture”, IEEE Computer Society Press, 1990, describe a boundary-scan architecture that—in principle—allows the testing of chip interconnections. One disadvantage of that architecture is, that it does not allow the simulation of high speed data links between chips.
In IBM Technical Disclosure Bulletin, Volume 34, No. 6, November 1991, pp. 325-330, by P. K. Graham an AC interconnect test with series boundary scan is described. If an interconnection between two IC chips is to be tested according to this method, first an enable signal is applied to the corresponding driver. After the enabled driver is switched on, a receiver clock is pulsed to capture the initialization values into the receiver latches. Only at this point, the timed portion begins. The B-clock of the system is pulsed to the driver data latch. Then, in a minimal, worst case-time after the B-clock, the receiver clock (C-clock) is pulsed to capture the driver data transitions in the receiver boundary latches. This is the end of the time portion. Thus this prior art test method does not provide for an interconnect test that simulates system operation in the functional mode. Other approaches are known from P.P. Fasang, “Microbit Brings Self-Testing on Board Complex Micro Computers”, Electronics, Mar. 10, 1982, pp. 116-119, and K. D. Wagner, T. W. Williams, “Enhanced Board Functional Self-Test by Concurrent Sampling”, International Test Conference 1991, pp. 633-640. Again these test methodologies do not provide for the simulation of high speed data links between chips that occur in the functional mode.
Another known technique for interconnect testing of chips is the usage of a circuit tester, whereby a test head is applied to the circuit under test. The test head has a “bed of nails”, i.e. a plurality of test needles serving to contact the circuit components under test. This technique is disadvantageous in that the testing frequency is restricted due to the usage of test needles and their associated capacitance and signal delay. A further problem of that technique is the mechanical tolerance of the test needles.
SUMMARY OF THE INVENTION
It is therefore a feature of the present invention to provide an improved test circuit, and method that allows interconnect testing of chips.
The invention is an electronic device having a test circuit to provide interconnect testing capability between first and second integrated circuits (ICs). The first IC has a first transceiver for providing an input and output operation, and a first storage device, electrically coupled to the first transceiver means, for storing test data. The second IC has a second transceiver means for providing an input and output operation. The test circuit specifically has a selector circuit, electrically coupled to the first and second transceivers, for 1) enabling the output operation of the first chip, and the input operation of the second chip, and 2) enabling a data link between the first and second transceiver means.
An additional feature of the invention is that the IC has a test data pattern generator, coupled to the first storage means, for generating a pattern of test data to be transferred and stored in the first storage means. In addition, the second IC has a second storage means, electrically coupled to the test data pattern generator via the first storage means, first transceiver means, second transceiver means. The second storage means is designed for storing test data received from test data pattern generator when the selector circuit 1) enables the output operation of the first chip, and the input operation of the second chip, and 2) enables the data link between the first and second transceiver means. Further, the second IC has a signature register means, coupled to the second storage means, for receiving and analyzing test data receiving from the second storage means.
An additional feature of the invention is that the selector circuit has a counter circuit that creates a counting signal. The counter circuit is coupled to a first decoder means, which is exclusively electrically coupled to the first transceiver means. The first decoder means receives counting signals and then forwards a first decoder signal to the first transceiver. In addition, the selector circuit has a second decoder means, exclusively electrically coupled to the second transceiver means, for receiving counting signals and then forwarding a second decoder signal to the second transceiver.
Other features and advantages of the present invention may become more clear from the following detailed description of the invention, taken in conjunction with the accompanying drawings and claims.
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Gruetzner Mathias
Hartmann Wilfred
Starke Cordt-Wilhelm
Baderman Scott T.
Beausoliel, Jr. Robert W.
International Business Machines - Corporation
Walsh Robert A.
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