Method for fabricating an isolation trench applied in BiCMOS...

Details Method for fabricating an isolation trench applied in BiCMOS... Method for fabricating an isolation trench applied in BiCMOS...

2000-05-22

2001-08-28

Nguyen, Tuan H. (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S202000, C438S234000

Reexamination Certificate

active

06281061

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for isolating, and more particularly to a method for fabricating an isolation trench applied in BiCMOS processes.
2. Description of the Prior Art
Referring to
FIG. 1
a
to
FIG. 1
e
to
FIG. 1
a
conventional method for fabricating an isolation trench applied in BiCMOS processes is schematically depicted in cross-sectional views.
Referring to
FIG. 1
a
, a semiconductor substrate
10
such as a P-type silicon substrate
10
is provided. Subsequently, a bipolar junction transistor region BJT, and MOS transistor regions T
1
and T
2
are defined by the conventional steps of forming a pre-doping oxide layer, alignment, and etching, wherein the MOS transistor region T
2
is formed between the bipolar junction transistor region BJT and the MOS transistor region T
1
. Thereafter, N
+
-type ions and P
+
-type ions are doped into the bipolar junction transistor region BJT and the MOS transistor region T
1
to form N
+
-type buried layers
12
and
16
, and to form a P
+
-type buried layer
14
in the MOS transistor region T
2
, respectively. An epitaxy layer
20
such as an N-type epitaxy layer is then formed on the silicon substrate
10
.
Referring to
FIG. 1
b
, N wells (N-W)
12
a
and
16
a
are formed in the epitaxy layer
20
above the N+-type buried layers
12
and
16
. For example, a pre-doping oxide layer
30
is formed on the epitaxy layer
20
by thermal oxidation. A photoresist layer (not shown) is then coated on the pre-doping oxide layer
30
, and a patterned photoresist layer PR
1
is formed by exposure and development steps, so that the pre-doping oxide layer
30
above the N
+
-type buried layers
12
and
16
is exposed. Subsequently, N wells (N-W)
12
a
and
16
a
are formed in the epitaxy layer
20
above the N
+
-type buried layers
12
and
16
by doping N-type ions into the epitaxy layer
20
Referring to
FIG. 1
c
, the photoresist layer PR
1
is removed, and a photoresist layer PR
2
is formed and patterned on the pre-doping oxide layer
30
so that the pre-doping oxide layer
30
above a region that is to be a collector region in the N well
12
a
is exposed. Subsequently, a collector region C is formed by doping N
+
-type ions into the N well
12
a.
Referring to
FIG. 1
d
, the patterned photoresist layer PR
2
and the pre-doping oxide layer
30
are removed, and a pad oxide layer
40
is then formed on the epitaxy layer
20
. Subsequently, a silicon nitride layer
50
is formed and defined by photolithography and etching processes to form openings
60
exposing the pad oxide layer
40
.
Referring to
FIG. 1
e
, a photoresist layer PR
3
is coated and patterned to expose the pad oxide layer
40
and the patterned silicon nitride layer
50
above a region that is to be a P well. Thereafter, a P well
14
a
is formed by doping P
+
-type ions into the epitaxy layer
20
above the P
+
-type buried layer
14
.
Referring to
FIG. 1
f
, the patterned photoresist layer PR
3
is removed, and field oxide layers
601
are formed in the openings
60
by local oxidation (LOCOS). Subsequently, the patterned silicon nitride layer
50
is removed.
The method as described above mainly utilizes the field oxide layer to isolate the N well, the collector region, and the P well, thereby decreasing the junction capacitance. However, the field oxide layer causes the Bird's Beak effect so that the integration of the semiconductor can't be increased. Furthermore, the isolating effect is poor.
SUMMARY OF THE INVENTION
Accordingly, the object of the present invention is to provide an isolating method that can solve the problems mentioned above.
To achieve the above-mentioned object, a method for fabricating an isolation trench applied in BiCMOS processes on a semiconductor substrate is provided. The method comprises the following steps: forming a first oxide layer on the semiconductor substrate to isolate a bipolar junction transistor (BJT) region, a first MOS transistor region, and a second MOS transistor region, wherein the second MOS transistor region is formed between the BJT region and the first MOS transistor region; forming a buried layer of a first conductivity type in the BJT region and the first MOS transistor region, and forming a buried layer of a second conductivity type in the second MOS transistor region; forming an epitaxy layer on the buried layers of the first and the second conductivity type, and forming a polysilicon layer on the first oxide layer; forming a second oxide layer on the polysilicon layer; forming a first well and a second well of a first conductivity type in the epitaxy layer above the BJT region and the first MOS transistor region; forming a collector region in the first well; forming a third well of a second conductivity type in the epitaxy layer above the second MOS transistor region; forming an etching stop layer on the second oxide layer, the first well and the second well, conformally; forming a first trench and a second trench exposing the surface of the first oxide layer by removing the etching stop layer, the second oxide layer, and the polysilicon layer, wherein the etching stop layer is formed above the second oxide layer, and forming a third trench by removing the etching stop layer adjacent to the collector region in the first well; filling a third oxide layer into the first, the second, and the third trench for isolating, and removing the remaining etching stop layer.


REFERENCES:
patent: 5057455 (1991-10-01), Foo et al.
patent: 5258318 (1993-11-01), Buti et al.
patent: 5356822 (1994-10-01), Lin et al.
patent: 5405790 (1995-04-01), Rahim et al.

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