Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-06-02
2001-03-20
Prenty, Mark V. (Department: 2822)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S331000
Reexamination Certificate
active
06204533
ABSTRACT:
BACKGROUND OF THE INVENTION
A power MOSFET is typically formed in a geometric pattern of cells. The cells may be in the shape of a closed figure such as a square or hexagon or they may comprise a series of parallel longitudinal stripes. The cell is defined at its perimeter by the gate electrode, and the interior of each cell normally contains a source diffusion and a body diffusion. In vertical power MOSFETs a single drain is normally located on the opposite side of the chip from the source and body and thus underlies the cells.
FIGS. 1A
,
1
B and
1
C illustrate overhead views of a single cell of a trench-gated MOSFET in a square, hexagonal and stripe configuration, respectively. In each figure, the outermost region represents one-half of the trenched gate (the other half belonging to the adjacent cell), the middle region represents the source region, and the innermost region represents the body contact region. The body region is in effect a continuation of the body contact region and extends under the source region to the sidewall of the trench, where the channel is located. The hatched regions represent the overlying metal source contact which in many power MOSFETs also contacts the body region to prevent the parasitic bipolar transistor from turning on.
The dimensions of each cell are defined by Ysb, which is the width of the source and body regions, i.e., the mesa inside the gate trench, and Yg, which is the width of the gate. As indicated, one-half of Yg is located on each side of the source/body region. The overall width or pitch of the cell is equal to Ysb+Yg.
The resistance of the MOSFET when it is turned on is directly related to the width of the channel, which lies along the wall of the trench. A figure of merit for a power MOSFET is the area/perimeter ratio or A/W, which is the amount of area that is required to provide a given channel width. Generally speaking, the lower the area/perimeter ratio, the lower the on-resistance of the MOSFET.
Using simple geometric formulas, the area and channel width (measured horizontally along the wall of the trench), and the resulting value of A/W, can be calculated for each of cells shown in
FIGS. 1A
,
1
B and
1
C.
For the square cell shown in FIG.
1
A:
A=(Ysb+Yg)
2
W=4·Ysb
and therefore
A
W
=
(
Ysb
+
Yg
)
2
4
·
Ysb
For the hexagonal cell shown in FIG.
1
B:
A
=
3
2
(
Ysb
+
Yg
)
2
W=2{square root over (3)}·Ysb
and
A
W
=
(
Ysb
+
Yg
)
2
4
·
Ysb
Finally, for the striped cell shown in FIG.
1
C:
A=(Ysb+Yg)·Z
W=2·Z
and
A
W
=
(
Ysb
+
Yg
)
2
or one-half of its cell pitch. Z, which is the length of the striped cell, drops out of the formula for A/W.
It is apparent from each of these equations that area/perimeter ratio A/W decreases with reductions in the cell pitch (Ysb+Yg).
FIG. 2
is a graph showing A/W as a function of cell density for three types of cells. Curve A represents A/W for a striped cell, curve B represents A/W for a square cell having a gate length Yg of 1 micron, and curve C represent A/W for a square cell having a gate length of 0.65 micron. Note that the cell density, which is measured in millions of cells per square inch, is intended to be a measure of the cell dimension that must be defined by photolithographic processes. Thus the density of the striped cells, in order to be equivalent to the density of the square cells, is figured on the basis of the number of square cells having a side dimension equal to the width of the stripe that would occupy a square inch. The corresponding cell pitch is shown at the top of the graph, a pitch of about 4.5 microns corresponding, for example, to a cell density of 32 Mcells/in
2
.
The current practical limit of cell density is in the neighborhood of 32 to 40 million cells/in
2
, corresponding to a cell pitch of about 4.5 microns and, for the square cell where Yg=1 micron, an A/W of about 1.44. In part, this limit arises because of the necessity of forming a body contact region within each cell to avoid parasitic bipolar turn-on, as shown in
FIGS. 1A-1C
. Another cause is the need to form a deep diffusion within each cell, as taught in U.S. Pat. No. 5,072,266 to Bulucea et al., to protect the gate oxide layer. In conduction, these factors place a lower limit on the lateral dimension of each cell and hence the cell density.
As indicated in
FIG. 2
, for cell densities less than 32-40 Mcells/in
2
the area/perimeter ratio of square cells is considerably lower than the area/perimeter ratio of striped cells. In fact, for striped cells a density of about 80 Mcells/in
2
is required to reach the A/W of 1.44 for square cells at a density of 32 Mcells/in
2
.
SUMMARY
In accordance with this invention a trench-gated power MOSFET having a cell density as high as 178 Mcells/in
2
is fabricated, using a striped cell geometry. As indicated in
FIG. 2
, this requires that the cell pitch be about 1.9 microns. This reduced cell pitch is obtained by forming the body contact region in various locations along the “stripe”. In one embodiment the body contact region is formed at the end of the stripe; in other embodiments the body contact region is formed at intervals along the stripe to limit resistive losses and consequent voltage drops from occurring between the source and body in portions of the striped cell.
Moreover, the gate oxide layer is protected by forming a deep diffusion at periodic intervals throughout the cell lattice, as taught in U.S. Patent application Ser. No. 08/459,555, filed Jun. 2, 1995, which is incorporated herein by reference in its entirety.
Using these techniques, the cell pitch can be reduced to about 1.9 microns, thereby reducing the area/perimeter ratio by a factor on the order of 36%.
REFERENCES:
patent: 5877538 (1999-03-01), Williams
patent: 5998836 (1999-12-01), Williams
patent: 5998837 (1999-12-01), Williams
Grabowski Wayne B.
Williams Richard K.
MacPherson Skjerven Morrill
Prenty Mark V.
Siliconix incorporated
Steuber David E.
LandOfFree
Vertical trench-gated power MOSFET having stripe geometry... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Vertical trench-gated power MOSFET having stripe geometry..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Vertical trench-gated power MOSFET having stripe geometry... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2474185