Method of forming a non-volatile memory device

Details Method of forming a non-volatile memory device Method of forming a non-volatile memory device

1998-12-18

2001-04-10

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S983000, C438S302000

Reexamination Certificate

active

06214666

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to non-volatile memory cells, and particularly non-volatile memory cells utilizing hot electron generation to add electrons to a floating gate.
2. Description of the Related Art
Non-volatile memory devices of the type commonly referred to in the art as EPROM, EEPROM, or Flash EEPROM serve a variety of purposes, and are hence provided in a variety of architectures and circuit structures.
As with many types of integrated circuit devices, some of the main objectives of non-volatile memory device designers are to increase the performance of devices, while decreasing device dimensions and consequently increasing circuit density. Cell designers strive for designs which are reliable, scalable, cost effective to manufacture and able to operate at lower power, in order for manufacturers to compete in the semiconductor industry. EEPROM devices are one such device that must meet these challenges. In some applications, such as flash memory cards, density is at a premium, while in applications such as programmable logic devices (PLD's), reliability is more important and space is at less of a premium.
As process technology moves toward the so-called 0.18 and 0.13 micron processes, the conventional “stacked gate” EEPROM structure has given way to different cell designs and array architectures, all intended to increase density and reliability in the resulting circuit. In addition, designers strive to reduce power requirements of devices by reducing program and erase voltage requirements.
In the self-aligned, “stacked gate” cell, a high quality oxide is required, as well as a unique drain and source structure optimized for program and erase operations, respectively, and complementary adaptive program and erase algorithms. Typically, in the stacked gate EEPROM, in order to store a logical zero, electrons are injected onto the floating gate to provide a negative voltage on the floating gate thus increasing the control gate threshold voltage needed to turn on the transistor. Likewise, in order to erase the EEPROM, electrons are removed from the floating gate thereby decreasing the threshold voltage and a logical one is stored on the gate. While stacked gate embodiments have existed and worked well for some time, improved alternative cells have resulted in higher performance integrated circuit devices.
One example of an alternative to the stacked gate EEPROM structure is shown in U.S. Pat. No. 4,924,278, issued to Stewart Logie on May 8, 1990 and assigned to the assignee of the present invention. The EEPROM structure disclosed therein utilizes a single layer of polycrystalline silicon so as to eliminate the need to form a separate control gate and floating gate. The EEPROM structure shown therein is made up of three separate NMOS transistors: a write transistor, a read transistor, and a sense transistor. In order to “program” the floating gate, a net positive charge is placed on the gate by removing free electrons from the floating gate. Likewise, to erase the floating gate, the floating gate is given a net negative charge by injecting electrons onto the floating gate. This basic EEPROM structure has been well exploited in commercial devices. Nevertheless, as process technologies and practical considerations drive designers toward higher performance, alternative designs are investigated. For example, the aforementioned cell structure requires, in a number of embodiments, a minimum oxide thickness of about 90 Å for the program junction oxide region to prevent charge loss due to direct tunneling under the presence of the high electric field across this region.
An alternative to the aforementioned Fowler-Nordheim tunneling-based cell structure is presented in Ranaweera, et al., “Performance Limitations of a Flash EEPROM Cell, Programmed With Zener Induced Hot Electrons,” University of Toronto Department of Electrical Engineering (1997). Discussed therein is a flash EEPROM cell which accomplishes programming and erase by establishing a reverse breakdown condition at the drain/substrate junction, generating hot electrons which are then coupled to the floating gate to program the cell.
FIGS. 1A
,
1
B and
1
C of Ranaweera, et al. are reproduced as
FIGS. 1A
,
1
B and
1
C of the present application.
FIGS. 1B and 1C
are cross-sections of the plan view of the cell shown in FIG.
1
A. As shown in
FIG. 1C
, a “ZEEPROM” cell comprises a source and drain region, floating gate and control gate, with a P+ pocket implant extending part way across the width of the drain region to generate hot electrons for programming. The flash ZEEPROM cells are fabricated using CMOS compatible process technology, with the addition of a heavily doped boron implant for the P+ region replacing or in addition to the LDD region. A sidewall spacer is necessary to form the self-aligned N+ source and drain regions and to avoid counter-doping of the P+ pocket.
To program the flash ZEEPROM cell, the PN junction is reverse-biased to create an electric field of approximately 10
6
volt/cm. and generate energetic hot electrons independent of the channel length. The P+ region adjacent to the drain enhances this generation. A low junction breakdown voltage can be used for programming by optimizing the PN junction depth and profiles. One disadvantage of this ZEEPROM is that a low drain voltage (approximately one volt) must be used to read the cell since the P+ region exhibits a low breakdown voltage which can contribute to “soft programming” due to unwanted charge injection to the gate (generally also referred to herein as “program disturb”). Erasing in the cell is performed by Fowler-Nordheim tunneling of electrons from the floating gate to the source region using a negative gate voltage and supply voltage connected to the source similar to conventional flash EEPROM cells.
Another alternative cell structure using hot election programming generated by a reverse breakdown condition at the drain is described in the context of a method for bulk charging and discharging of an array of flash EEPROM memory cells in U.S. Pat. No. 5,491,657 issued to Haddad, et al., assigned to the assignee of the present invention. In Haddad, et al., a cell structure similar to that shown in cross-section in
FIG. 1B
of the present application may be used, as well as a substrate-biased p-well in n-well embodiment. In the first embodiment, an N+ source region includes an N+ implant region and an N diffusion region, and the erase (removing electrons) operation is accomplished by applying (+)8.5 volts to the control gate for 100 milliseconds, and (+)5 volts to the source for 100 milliseconds, with the drain being allowed to float. In contrast, programming (adding electrons to the gate) is achieved by applying a negative 8.5 volt to the substrate for 5 microseconds, zero volts to the drain and control gate with the source floating. The bulk charging operation can just as easily be done on the source side rather than the drain side in a case where the cell is provided in a P well by applying −8.5 volts to the P well for 5 microseconds, 0 volts to the source and control gate with the drain being allowed to float.
Yet another structure and method for programming a cell is detailed in co-pending U.S. patent application Ser. No. 08/871,589, inventors Hao Fang, et al., filed Jul. 24, 1998 and assigned to the assignee of the present application.
FIGS. 1A and 1B
of the Fang, et al. application are reproduced herein as
FIGS. 2A and 2B
, and
FIGS. 2A and 2B
of the Fang application are reproduced as
FIGS. 3A and 3B
of the present application. The Fang, et al. application uses the programming method disclosed in Haddad, et al. to form a high density, low program/erase voltage and current, and fast byte programming and bulk-erase and fast reading speed non-volatile memory structure specifically designed for programmable logic circuit applications.
In Fang, et al. the non-volatile memory cell
10
in
FIG. 2A
,
2
B is formed of a

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