Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-01-21
2001-06-26
Utech, Benjamin L. (Department: 1765)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000, C438S719000, C438S723000, C438S395000
Reexamination Certificate
active
06251726
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the fabrication semiconductor integrated circuits, and more particularly to a method of fabricating random access memory (DRAM) devices, having stacked capacitors with an additional polysilicon plug to reduce the aspect ratio for capacitor node contact openings while increasing capacitance.
(2) Description of the Prior Art
Advances in Ultra Large Scale Integration (ULSI) technologies are dramatically increasing the circuit density on the semiconductor chip. This increase in density is due in part to advances in high-resolution photolithography and anisotropic plasma etching in which the directional ion etching results in essentially bias-free replication of the photoresist image in the underlying patterned layers, such as in polysilicon and insulating oxide layers and the like.
One such circuit type where this high-resolution processing is of particular importance is the dynamic random access memory (DRAM) circuit. This DRAM circuit is used extensively in the electronics industry, and particularly in the computer industry for electrical data storage. The DRAM circuits consist of an array of individual memory cells, each cell consisting of an access transistor, usually a field effect transistor (FET), and a single storage capacitor. Information is stored on the cell as charge on the capacitor, which represents a unit of data (bit), and is accessed by read/write circuits on the periphery of the DRAM chip. After the year 2000 the number of these cells on a DRAM chip is expected to exceed a gigabit. To achieve this high density and still maintain a reasonable chip size, the individual cells on the chip must be significantly reduced in size. As these individual memory cells decrease in size, so must the area on the cell that the storage capacitor occupies. The reduction in the storage capacitor size makes it difficult to store sufficient charge on the capacitor to maintain an acceptable signal-to-noise level, and circuits require shorter refresh cycle times to retain the necessary charge level. One method of overcoming this size problem is to build stacked capacitors that extend vertically over the cell areas to increase the electrode capacitor area while confining the capacitor within the cell area.
However, as the minimum feature sizes decrease to less than a quarter-micrometer (0.25 um), it becomes increasing difficult to built reliable stacked capacitors without increasing process complexity and manufacturing cost. One process complexity is the need to etch contact holes in insulators with increasing aspect ratios (depth/width). It is difficult to etch these deep holes without over-etching that damages the substrate causing excessive junction leakage at the capacitor node contact.
For these submicrometer devices it is also important to provide planar surfaces to facilitate the formation of high resolution photoresist etch masks that require a more shallow depth of focus (DOF) during the photoresist exposure. Planar surfaces are also required because of the very directional etching, since patterning layers, such as polysilicon and metals, by directional etching can otherwise result in unwanted residue at steps (recesses) on non-planar surfaces. However, planarizing process, such as chemical-mechanical polishing or planarizing etch backs, are time consuming and costly. Therefore it is desirable to minimize the number of planarizing steps and to reduce the aspect ratio for contact holes on DRAM circuits.
Numerous methods of making DRAM circuits with stacked capacitors having increased capacitance have been reported in the literature. The following U.S. patents describe several methods for making stacked capacitors. Wang et al. in U.S. Pat. No. 5,702,989 describe a method for making a DRAM using a single polysilicon plug as the capacitor node contact and also serves as a center column in the capacitor to increase capacitance. However, this single plug requires etching very deep contact contacts with very high aspect ratios (depth/width) and is difficult to achieve without excessive over etching in the insulating layer. Another approach is described by Chao in U.S. Pat. No. 5,863,821 in which a contact hole is etched through a multilayer to the substrate. This is also difficult to achieve without over-etching. Tseng in U.S. Pat. Nos. 5,854,105 and 5,843,821 describe methods for making DRAMs with single polysilicon plugs in a planar insulating on which are fabricated stacked capacitors. However, further process would require an insulating layer over the capacitors that would need to be planarized. In U.S. Pat. No. 5,888,865 Lin describes a method for making a DRAM capacitor using a single polysilicon plug that also serves as a portion of the stacked capacitor. However, Lin etches contact holes through a relatively thick multilayer to the substrate which can result in over-etch and substrate damage (leakage currents).
However, there is still a need to improve the fabrication of DRAM devices with high capacitance for future product generation below the 0.25 um feature sizes and to make the process more manufacturable and cost effective.
SUMMARY OF THE INVENTION
It is a principal object of the present invention to provide a method for fabricating DRAM memory cells with stacked capacitors having increased capacitance that are more manufacturable and cost effective.
It is another object of this invention to achieve the principal object above by using an additional second (upper) polysilicon plug, as a pillar, that is aligned over a first (bottom) polysilicon plug used as the capacitor node contact. The use of two polysilicon plug reduces the etch depth of the contact openings for better control when making sub-quarter micrometer (<0.25 um) DRAM product. This additional pillar also results in increased capacitor height (increased capacitance) with excellent capacitance control while avoiding plasma etch damage to the substrate in the node contact openings.
It is still another object of this invention to use this additional upper polysilicon plug to independently optimize the total surface area for capacitor enhancement of future product generation beyond 0.25 um without the need to alter (disturb) the underlying DRAM structure.
The above objects of this invention are achieve by first providing a semiconductor substrate (wafer) composed of single crystalline silicon. A field oxide is formed in and on the substrate surrounding and electrically isolating an array of device areas in which are formed the semi-conductor devices. The most commonly used devices are field effect transistors (FETs). For high density circuits a more advanced field oxide isolation is utilizes, commonly referred to a shallow trench isolation (STI). The STI is formed by etching a shallow trench in the silicon substrate and filling the trench with an insulating material, such as a chemical vapor deposited (CVD) silicon oxide (SiO
2
). The SiO
2
is polished or etched back to form a STI that is planar with the substrate surface. The FETs are formed by first forming a thin gate oxide on the device areas. A conductively doped polysilicon layer and a silicide layer are deposited to form a polycide layer. The polycide layer is then patterned to form word lines for the DRAM cells, and portions of the patterned polycide extend over the device areas and serve as the FET gate electrodes. Concurrently the patterned polycide layer also serves as local inter-connection for the peripheral circuits on the DRAM chip. Lightly doped drains (LDDs) are formed next in the substrate adjacent to the gate electrodes, usually by ion implantation, and sidewall spacers are formed on the gate electrodes by depositing and blanket etching back an insulating layer, such as SiO
2
or SiO
2
and Si
3
N
4
. After the LDDs and sidewall spacers are formed, the FETs in the peripheral circuits are completed by forming heavily doped source/drain contact regions adjacent to the sidewall spacer to provide low contact resistance.
Continuing with the process, the improved
Ackerman Stephen B.
Deo Duy-Vu
Saile George O.
Taiwan Semiconductor Manufacturing Company
Utech Benjamin L.
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