Transistor of SIC

Details Transistor of SIC Transistor of SIC

1998-02-06

2001-03-13

Tran, Minh Loan (Department: 2811)

Active solid-state devices (e.g., transistors, solid-state diode

Field effect device

Having insulated electrode

C257S331000, C257S342000

Reexamination Certificate

active

06201280

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a transistor of SiC for high voltage and high switching frequency applications having an insulated gate and being one of a) a MISFET and b) an IGBT, the transistor comprising, superimposed on each other in the following order: a drain; a highly doped substrate layer being for a) of n-type and for b) of p-type, for b) on top thereof one of c) a highly doped n-type buffer layer and d) no such layer; and a low doped n-type drift layer; the transistor further comprising a plurality of laterally spaced unit cells each having a highly doped n-type source region layer, a source arranged on top of the source region layer, a p-type channel region layer separating the source region layer from the drift layer, an insulating layer located next to the channel region layer and extending from the source region layer to the drift layer and to the channel region layer and the source region layer of an adjacent unit cell and a gate electrode arranged on the insulating layer and adapted to form a conducting inversion channel extending in the channel region layer at the interface to the insulating layer for electron transport from the source to the drain upon applying a voltage thereto, the center to center distance of two adjacent unit cells defining a lateral width of a unit cell of the transistor.
The accumulation region is defined for instance by Baliga in “Modern Power Devices” (John Wiley & Sons, Inc, 1996) on page 369. In Si transistors having an insulated gate, such as MOSFETs, the design is mainly directed towards achieving as low specific on-resistance as possible, since power losses emanating from switching are almost neglectable with respect to the on-state conducting loses in the case of the relatively low blocking voltages in such devices of Si. Furthermore, the high on-resistance in Si devices is the main obstacle in realizing devices for higher voltages. For this reason, it is most frequently a desire to keep the cell pitch, i.e. the center to center distance of two adjacent unit cells, as small as possible in order to increase the packing density and thus reduce the on-resistance. This is possible to do in the trench type of devices without other than technological limitations but in the DMOS type of devices the on-state voltage increases again as the cells are put too close together due to the so called JFET effect which is the increase in vertical resistivity between the adjacent p-base regions belonging to the neighboring cells. For a determined lateral cell width it is also aimed at having an accumulation region with a lateral width being as large as possible, since it is understood that the on-state voltage does decrease with increasing ratio of accumulation region width to the total cell width.
Gate-controlled transistors, such as MOSFETs, of SiC have the operating potential at much higher voltages than those of Si. This is mainly due to much lower specific on-resistance of the drift region for a given voltage (200 times lower for 1 kV devices) compared to Si. However, with increasing voltage the importance of the switching losses increases. The switching losses in gate-controlled transistors of SiC have to be considered in a new and more careful way than what was the case so far, especially for high voltage and high switching frequency applications, since the power losses relating to the switching may otherwise strongly limit the performance and the applicability of such a semiconductor device.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a transistor of SiC having an insulated gate which makes it possible to better benefit from the superior property of SiC with respect to Si making operations at much higher voltages possible without being substantially limited by high switching losses.
This object, according to the invention, is obtained by providing a transistor in which the relation of lateral width of an accumulation region, defined as the region in the drift layer connecting to the insulating layer in each individual cell, and the lateral cell width is selected so as to minimize the total power losses in the transistor and to keep the power losses in the transistor as a consequence of switching in a certain determined proportion to the power losses relating to conduction of the transistor for a predetermined switching frequency for which the transistor is designed.
Due to this new “design rule” it will be possible to provide transistors if SiC for high voltage and high switching frequency applications operating while dissipating power at an acceptable low level under these conditions. It is a totally new concept for these types of transistors of SiC to vary the relation of the lateral width of the accumulation region and the lateral cell width to keep the power losses in the transistor due to switching at an acceptable low level with respect to the conduction losses, since it has probably been found more natural to vary the doping concentration of the drift layer or other parameters for this purpose. This type of selection is not known, either, to transistors of Si for which it has generally been an aim to make the lateral cell width as small as possible and the lateral width of the accumulation region as large as possible for a given lateral cell width, for obtaining as low specific on-state resistance as possible without concern for the small losses emanating from the switching. The same design rule applies also to Si devices or devices made of any other semiconducting material. However, the effect it has on both on-state voltage and switching losses depends on the doping density in the drift layer. This limits the design voltage range in which the rule is most efficient to below 4.5 kV in the case of Silicon but well above 25 kV in the case of SiC, as will be discussed below. The attractiveness of the design rule for the high voltage devices is thus significantly greater in the case of SiC.
According to a preferred embodiment of the invention the relation of the lateral width of the accumulation region and the lateral cell width is selected to obtain lower total power losses in the transistor as a consequence of both conduction and switching of the transistor and a desired relation of the conduction and switching losses to the total losses for a predetermined switching frequency. With a conventional design of such a transistor, namely with a lateral width of the accumulation region being as large as possible for a given lateral cell width, it was until now impossible to obtain lower power losses resulting from switching than those as a consequence of conduction for higher switching frequencies, but the selection of the relation of the lateral width of the accumulation region and the lateral cell width according to the invention makes this surprisingly possible.
According to another preferred embodiment of the invention the lateral width of the accumulation region is smaller than or equal to half the lateral cell width. This way of aiming at decreasing the quotient lateral width of the accumulation region/lateral cell width for keeping the power losses emanating from switching on an acceptable low level is a totally new approach to this problem within this technique, and it drastically improves the prospects of obtaining transistors of SiC for high voltage and high switching frequency applications without too high losses emanating from the switching. Thus, the present invention goes in the opposite direction of that in Si devices, in which it is natural to increase the lateral width of the accumulation region when this is possible, such as when the lateral cell width is increased. The present inventors have realized that the properties of SiC make it possible and highly desirable to take such measures. The doping concentration of the drift layer may in SiC devices be made much higher (by two orders of magnitude) than in Si due to the higher dielectric strength of SiC. This allows the reduction of the required width of the drift layer by one order of magnitude and makes it pos

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