Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-11-12
2001-04-17
Nelms, David (Department: 2818)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S398000, 43
Reexamination Certificate
active
06218230
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for producing a capacitor, and in particular to a method for producing a capacitor in which hemispherical grain (HSG) is formed on the surface of its lower electrode.
2. Related Art
A stacked capacitor using an amorphous silicon film as an electrode has widely been used as a DRAM cell from 1 MB DRAM times to the present time. However, in its conventional structure, it is becoming difficult to keep its capacitance sufficient by reduction in cell size accompanying a rise in integration degree. Thus, methods for increasing the surface area of a lower electrode (the area opposite to an upper electrode) effectively have been studied, for example, a method of making the lower electrode into a cylindrical form, or a method of forming HSG on the surface of the electrode.
Conventional examples of methods for producing such a capacitor are shown in
FIGS. 3 and 4
.
An example of a method for producing a cylindrical stacked capacitor is shown in FIGS.
3
(
a
) and
3
(
b
). First, a phosphorus-doped amorphous silicon layer
38
is grown so that it connects to a drain area (not illustrated) through a node contact hole
37
, and then this layer is etched to be into a cylindrical form (FIG.
3
(
a
)). Thereafter, its surface is irradiated with a silicon molecule beam or the like to form nuclei for HSG growth, and the resultant is annealed to grow HSG
39
(FIG.
3
(
b
)), causing formation of a lower electrode.
Another example of a method for producing a capacitor having a step to deposit a double-layer film is shown in FIGS.
4
(
a
) to
4
(
c
). First, a phosphorus-doped amorphous silicon layer
42
is grown so that it connects to a drain area (not illustrated) through a node contact hole
41
, and then this layer is etched to be into a cylindrical form (FIG.
4
(
a
)). Subsequently, a non-doped silicon layer
43
is grown on the entire surface thereof (FIG.
4
(
b
)). Next, using this non-doped silicon layer as a base, a silicon molecular beam is applied to this layer, to form nuclei for HSG growth, and then annealing treatment is carried out to form HSG
44
. Thereafter, the resultant is subjected to etch back treatment to isolate a stack electrode, and then is subjected to annealing treatment to form a lower electrode (FIG.
4
(
c
)).
In the first prior art, the lower electrode is in a cylindrical form. Thus, the absolute amount of the impurity is liable to become insufficient and after formation of the HSG the impurity of a sufficient concentration is not diffused into the grown HSG portions, causing the problem of depletion easily. In order to avoid this problem of depletion, it is necessary to raise the impurity concentration in the doped silicon layer, which is a base for formation of the HSG. In this case, however, the growth rate of the HSG drops. In particular, if the impurity concentration is made higher than a given level, the problem arises that the HSG is hardly formed. This would probably be because phosphorus is precipitated on the surface of the doped silicon, not permitting surface migration of silicon. Besides, there is room for improvement, from the standpoint that parameters for deciding density and size of the HSG cannot be sufficiently freely selected.
In the second prior art, a non-doped silicon layer is deposited on the entire surface of a phosphorus-doped silicon layer and, consequently, it is necessary that after the growth of HSG etch back treating is carried out for separation of respective electrodes. At this time, the most serious problem arises that the HSG and the cylindrical portion itself are damaged. If the non-doped silicon layer is selectively formed, the etch back treatment is unnecessary. In this case, however, the problem arises that the thickness of the non-doped silicon layer is limited. Specifically, if the thickness of the film becomes large, selectivity is lost in growth of the non-doped silicon layer, causing a short circuit between electrodes. For this reason, it is necessary that the layer thickness is usually 15 nm or less. Therefore, HSG having a sufficient size may not be obtained.
SUMMARY OF THE INVENTION
To overcome the aforementioned problems in producing a lower electrode whose surface has HSG, an object of the present invention is to realize a capacitor having a high capacitance by controlling the size of the HSG appropriately and uniformly and preventing depletion of impurities.
The method for producing a capacitor of the present invention comprises the step of forming a first amorphous silicon layer; the step of forming a second amorphous silicon layer on the first amorphous silicon layer; and the step of growing hemispherical grain (HSG) on a surface of the second amorphous silicon layer, using the first amorphous silicon layer as a stopper of the growth.
Since the first amorphous silicon layer functions as a stopper for preventing the HSG from growing up to undesirably larger size, the shape of the HSG can be kept satisfactory.
Furthermore, by making the impurity concentration in the first amorphous silicon layer lower than that in the second amorphous silicon layer, the second amorphous silicon layer becomes a source for supplying silicon for the HSG growth, and the first amorphous silicon layer becomes a source for supplying an impurity for giving conductivity to the HSG, causing the growth rate of the HSG to be improved. In addition, the HSG having good property can be formed since the impurity can easily diffuse into the HSG.
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Fujiwara Shuji
Hirota Toshiyuki
Dang Phuc T.
Foley & Lardner
NEC Corporation
Nelms David
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