Electrical computers and digital processing systems: support – Synchronization of clock or timing signals – data – or pulses
Reexamination Certificate
1998-07-02
2001-03-13
Lee, Thomas C. (Department: 2787)
Electrical computers and digital processing systems: support
Synchronization of clock or timing signals, data, or pulses
C713S501000, C713S600000
Reexamination Certificate
active
06202164
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to computer systems and, more particularly, to synchronizing clocks within computer systems.
2. Description of the Related Art
Computer systems, such as personal computer systems, were originally developed for business applications such as word processing, databases and spread sheets, among others. Computer systems, however, are currently being used to handle a number of isochronous tasks including: multimedia applications having video and audio components, video capture and playback, telephony applications, and speech recognition and synthesis, among others. Generally speaking, isochronous tasks are time-dependent tasks. In other words, the data handled by an isochronous task must be delivered or processed within certain time constraints.
One problem that has arisen is that computer systems originally designed for business applications are not well suited to the time-dependent requirements of modern multimedia applications. For example, modern computer system architectures still presume that the majority of applications executed are business applications, such as word processing or spread sheet applications. Typical computer systems are inefficient at handling streams of time-dependent data, or isochronous data, that make up multimedia data types. The isochronous data of multimedia tasks require the maintenance of a temporal component. For example, audio signals may be coded as a stream of samples taken at a consistent sampling rate. The temporal relationship between these samples must be maintained to prevent perceptible errors such as gaps or altered frequencies. Likewise, the loss of the temporal relationship in a video signal can cause blank screens or lines.
To accommodate isochronous data, computer systems typically employ one or more data buses configured to handle the transfer of isochonrous data. Examples of these data buses include the Universal Serial Bus (USB), the IEEE 1394 bus, and the Audio Codec '97 (AC '97) bus. Unfortunately, the isochronous buses of a computer system are typically independently designed. Accordingly, the buses may have independent data rates. Further, even buses with a common data rate and devices coupled to those buses typically have independent clocks that drift relative to each other. These differences in clock rates create discrepancies in the rates at which data is generated and consumed.
Typical computer systems include buffers to accommodate the lack of synchronization and drift between the clocks of a computer system. Unfortunately, buffers add expense, size, and latency to computer systems. Therefore, it is desirable to reduce the size of the buffers within computer systems.
What is desired is a clock structure in which the various clocks of the data buses and/or devices coupled to those buses within the computer system are synchronized.
SUMMARY OF THE INVENTION
The problems outlined above are in large part solved by a master isochronous clock structure in accordance with the present invention. In one embodiment, a frame-rate clock of a plurality of data buses are synchronized to a master clock signal. The master clock signal may be derived from the existing clocks signals within the computer system or from data received from an external source. The master clock signal may also be used by an operating system scheduler to schedule task that generate or consume blocks of isochronous data.
In an alternative embodiment, the drift of a device clock signal relative to a master clock signal is measured and used to synchronize the device clock signal. For example, a mechanism may monitor the level of data in a data buffer. The level of data in the data buffer is a measure of the drift between the clock generating the data and the clock consuming the data. Based upon the level of data in the buffer, synchronization information is provided to synchronize the rates of the clock signals that generate and consume the data. In one embodiment, the level of data in a data buffer is used to synchronize the clock of a video camera. In another embodiment, the level of data in a data buffer is used to synchronize a clock of a telephony codec.
Broadly speaking, the present invention contemplates a computer system including: a central processing unit (CPU), a data buffer operably coupled to the CPU, a clock controller coupled to the data buffer, and a video camera operably coupled to the data buffer. The CPU is configured to read data from the data buffer at a first predetermined clock rate. The clock controller is configured to monitor levels of data in the data buffer, and to provide a signal indicative of the levels of data. The video camera is configured to generate the data and write the data to the data buffer at a second predetermined clock rate. The video camera in coupled to a clock that includes a data clock configured to provide a data clock signal, and a programmable clock divider coupled to the data clock. The second predetermined clock rate is generated by programming a value into the programmable clock divider and dividing the data clock by the value. The value is programmed responsive to the clock controller determining that the levels of data in the data buffer cross a predetermined threshold, such that the second predetermined clock rate approximates the first predetermined clock rate.
The present invention further contemplates a computer system including: a central processing unit (CPU), a data buffer operably coupled to the CPU, a clock controller coupled to the data buffer, a telephony codec operably coupled to the data buffer, and a telephony device operably coupled to the telephony codec. The CPU is configured to read data from the data buffer at a first predetermined clock rate. The clock controller is configured to monitor levels of data in the data buffer and to provide a signal indicative of the levels of data. The telephony device is configured to generate the data, and the telephony codec is configured to write the data to the data buffer at a second predetermined clock rate. The telephony codec includes a data clock configured to provide a data clock signal, and a programmable clock divider coupled to the data clock. The second predetermined clock rate is generated by programming a value into the programmable clock divider and dividing the data clock by the value. The value is programmed responsive to the clock controller determining that the levels of data in the data buffer cross a predetermined threshold, such that the second predetermined clock rate approximates the first predetermined clock rate.
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Advanced Micro Devices , Inc.
Conley Rose & Tayon PC
Kivlin B. Noäl
Lee Thomas C.
Omar Omar A.
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