Metallization technique for gate electrodes and local...

Details Metallization technique for gate electrodes and local... Metallization technique for gate electrodes and local...

1997-06-30

2001-03-27

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S587000, C438S588000, C438S591000, C438S592000, C438S618000

Reexamination Certificate

active

06207543

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to processing of a semiconductor device, and more particularly, but not exclusively relates to a technique to provide metallization for interconnecting local connection regions along the substrate of a semiconductor device and simultaneously forming gate electrodes.
Most Integrated Circuits (ICs) require some type of metallic interconnection. For highly integrated semiconductors, these interconnections are often provided by depositing an Intermetal Oxide (IMO) layer over a semiconductor substrate bearing the various components to be interconnected, and then etching a via hole through the oxide layer to form a metallic contact with the contact region of each component. These metal contact vias are typically connected by metal lines formed on the top side of the IMO in accordance with a routing pattern. When extensive interconnections are required, connection routing on the top side of the IMO layer may become complex. Also, the smaller semiconductor component features become, the more difficult it is to properly align a large number of contact vias. This problem is particularly prominent in the development of ICs with high density Random Access Memory (RAM).
Thus, a need exists to reduce IC interconnection routing complexity and the number of interconnecting contact vias required. The present invention satisfies this need and provides other significant benefits and advantages.
SUMMARY OF THE INVENTION
The present invention relates to the manufacture of semiconductor devices. Various aspects of the invention are novel, non-obvious, and provide various advantages. While the actual nature of the invention covered herein may only be determined with reference to the claims appended hereto, certain aspects which are characteristic of the preferred embodiments disclosed herein are described briefly as follows.
One aspect of the present invention is the interconnection of semiconductor contact regions that are close to each other along a semiconductor substrate without routing over an intervening intermetal oxide layer. This aspect of the present invention reduces the number of vias, and resulting topside interconnections required to facilitate higher device density. The regions may be interconnected by applying a contact metal that is simultaneously utilized to metallize gate electrodes.
In a further aspect, a process for making an IC includes coating a number of integrated circuit components positioned along a semiconductor substrate with a dielectric layer, planarizing the dielectric layer, then forming a trench in the dielectric layer to expose a pair of contact regions. This trench is filled with a metal, such as tungsten, to provide an electrical interconnection between the contact regions. The metal is then planarized to be approximately coplanar with the planarized oxide layer. Metal gate electrodes may be formed at the same time as the interconnection. This process reduces the number of contacts and connections required to be routed through or on an IMO layer.
In another aspect, a process for manufacturing an integrated circuit includes defining a region of a silicon substrate for formation of a first field effect transistor with a first source and a first polysilicon gate adjacent a second field effect transistor with a second source and a second polysilicon gate. The first and second transistors share a common drain. The first and second polysilicon gates are spaced apart from one another to define a gap therebetween. The process also includes depositing a silicon dioxide layer on the region to fill this gap, and removing a portion of the silicon dioxide layer by chemical mechanical polishing to expose a portion of the polysilicon gate for each of the pair of transistors; thereby defining a first generally planar surface. The first and second polysilicon gates are etched to define a first recess in the first polysilicon gate and a second recess in the second polysilicon gate. A photoresist pattern is established on the region that defines an opening over the common drain and at least a portion of the first recess. A portion of the silicon dioxide layer corresponding to the opening is selectively etched to define a third recess exposing at least a portion of the common drain and the photoresist pattern is removed. The process additionally includes covering the region with a metallic layer that fills the first, second, and third recesses and planarizing the region by removing a portion of the metallic layer to define a second generally planar surface. This second surface includes a first metallic region interconnecting the first gate and the common drain, a second metallic region provided by metal in the second recess, and an oxide region positioned between the first and second metallic regions. Formation of the first and second field effect transistors is then completed.
In a further aspect of the present invention, a number of semiconductor device features are formed that extend from a semiconductor substrate. These features are spaced apart from each other to define a corresponding number of gaps therebetween. The features and the substrate are coated. The resulting coating occupies at least a portion of each of the gaps. A portion of the coating farthest away from the substrate is removed by chemical-mechanical polishing to expose each of the features. A self-aligned process is performed with the features exposed by the removal. The features may be transistor gates.
An additional aspect of the present invention includes: (a) forming a semiconductor device feature that extends from a semiconductor substrate; (b) covering the feature and the substrate with a coating; (c) removing a part of the coating farthest away from the substrate to form a generally planar region along the coating and expose the feature; and (d) performing a self-aligned process to the exposed feature. The removal of coating may include the removal of part of the feature to define a feature surface and a coating surface that are generally coplanar. Also, the feature may include a polysilicon member of a field effect transistor gate.
Accordingly, it is one object of the present invention to provide a technique for locally interconnecting contact regions of components of a semicondutor device.
An additional object is to provide integrated circuit component interconnections that need not be routed through or on an IMO layer.
It is another object of the present invention to simultaneously form transistor gate electrodes and local device interconnect metallization.


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