Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1999-07-02
2001-06-26
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S481000, C438S006000, C438S607000
Reexamination Certificate
active
06251769
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of manufacturing a semiconductor device. More particularly, the present invention relates to a method of manufacturing a contact pad.
2. Description of Related Art
Currently, the aspect ratio of a node contact hole and a contact hole is increased as the integration of the integrated circuit is increased, so that it is difficult to open the node contact hole and the contact hole in a photolithography and etching process. Hence, a contact pad formed on a source/drain region is used as a contact medium between the source/drain region and a node contact (or a contact) to overcome the problem of opening the node contact hole or the contact hole.
FIGS. 1A through 1D
are schematic, cross-sectional views of the conventional process for manufacturing a node contact hole.
As shown in
FIG. 1A
, a substrate
100
having a shallow trench isolation (STI)
102
, a source/drain region
104
, a gate structure
106
and an inter-layer dielectric (ILD) layer
108
is provided. The STI
102
is formed in the substrate
100
. The gate structure
106
is formed on the substrate
100
and the source/drain regions
104
are formed in the substrate
100
exposed by the gate structure
106
. The ILD layer
108
is formed over the substrate
100
. An opening
110
is formed in the ILD layer
108
and exposes a portion of the source/drain region
104
. A polysilicon layer
112
is formed over the substrate
100
and fills the opening
110
.
As shown in
FIG. 1B
, a portion of the polysilicon layer
112
is removed by chemical-mechanical polishing (CMP) or etching back to expose the surface of the ILD layer
108
. The remaining polysilicon layer
112
forms a contact pad
112
a
. An interpoly dielectric layer (IPD)
114
is formed over the substrate
100
.
As shown in
FIG. 1C
, a bit-line opening
116
is formed to penetrate through the IPD layer
114
and the ILD layer
108
and exposes a portion of the source/drain region
104
. A polysilicon layer (not shown) is formed over the substrate
100
and fills the bit-line opening
116
. The polysilicon layer is patterned to form a bit line
116
a
in the bit-line opening
116
.
As shown in
FIG. 1D
, a dielectric layer
118
is formed over the substrate
100
. A node contact hole
120
aligned with the contact pad
112
a
is formed to penetrate through the dielectric layer
118
and the IPD layer
114
and exposes the contact pad
112
a.
While the node contact hole is formed, misalignment may occur, as shown in FIG.
2
. In
FIG. 2
, an opening formed when misalignment occurs is denoted by
222
, while the reference numbers of the other components are the same as that in
FIG. 1D
since the manufacturing procedure of those components are the same as that illustrated by FIG.
1
D. Because the opening
222
merely exposes a portion of the contact pad
112
, the contact area between the contact pad
112
and the subsequently formed node contact is relatively small. Hence, the contact resistance between the contact pad
112
and the subsequently formed node contact is increased. Additionally, the materials of the dielectric layer
118
, the IPD layer
114
and ILD layer
108
are similar to each other, so the etching depth cannot be easily controlled and the opening
222
easily penetrates through the IPD layer
114
and into the ILD
108
to form a trench
222
a
adjacent to the contact pad
112
a
. Moreover, in the subsequent formation of the node contact in the node contact hole, it is difficult to fill the trench
222
a
with polysilicon material, so that a void is formed in the trench
222
a
. These conditions lead to electrical failure of the device. Typically, in order to overcome the problem caused by the misalignment of the node contact hole, the size of the node contact hole is decreased to avoid the formation of the node contact hole from misalignment. However, the contact area between the contact pad and the subsequently formed node contact is decreased due to the decreasing of the size of the node contact hole, so that contact resistance is increased.
SUMMARY OF THE INVENTION
The invention provides an improved method of manufacturing a contact pad. A substrate having a source/drain region formed therein is provided. A dielectric layer is formed over the substrate. An opening is formed in the dielectric layer and exposes the source/drain region. A selective epitaxial process is performed to form a contact pad in the opening, wherein a top of the contact pad extends onto a surface of the dielectric layer. A gas source of the selective epitaxial process includes Si
x
H
y
/HCl or Si
x
H
y
Cl
z
/HCl. While the selective epitaxial process is performed, an in situ doping process is simultaneously performed by adding doping gases (PH
3
or AsH
3
etc.).
The invention provides a method of manufacturing a semiconductor device. A substrate having a gate structure formed thereon and a source/drain region formed therein under the gate structure is provided. A first dielectric layer is formed over the substrate. An opening is formed in the first dielectric layer to expose the source/drain region. A selective epitaxial process is performed to form a contact pad in the opening, wherein a top of the contact pad extends onto a surface of the first dielectric layer. A second dielectric layer is formed over the substrate. A node contact hole is formed in the second dielectric layer to expose the contact pad.
Since the top of the contact pad extends onto the surface of the first dielectric layer to form a T shaped contact pad, the area of the top of the contact pad is relatively large. Therefore, the contact resistance is not increased. Additionally, etching rates of the contact pad and the first dielectric layer are different, the etching stopped on the contact pad can be well controlled while misalignment occurs. Moreover, the contact pad is formed by a selective epitaxial process, so that the cost is decreased.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 4745081 (1988-05-01), Beyer et al.
Huang Kuo-Tai
Lur Water
Yew Tri-Rung
Bowers Charles
Huynh Yennhu B.
United Microelectronics Corp
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