Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-05-27
2001-03-27
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S396000, C438S399000
Reexamination Certificate
active
06207499
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having a semiconductor substrate such as a GaAs substrate and a capacitor formed thereon, a method of fabricating it, and a sputtering apparatus suited to this fabrication method.
Conventional capacitors known in the art include, for example, MIM (Metal-Insulator-Metal) capacitors wherein a dielectric material is sandwiched between two metal electrodes and Schottky capacitors which use Schottky barrier capacitance.
The capacitance C of a MIM capacitor may be expressed in terms of the following equation, where &egr;
0
denotes a dielectric constant of vacuum, &egr;
r
denotes a dielectric constant of the dielectric material, S denotes a surface area of the capacitor, and d denotes a distance between the electrodes.
C=&egr;
0
&egr;
r
(
S/d
)
To fabricate a capacitor of high capacitance, a dielectric material of high dielectric constant &egr;
r
may be used, the distance d between the electrodes may be reduced, or the capacitor surface area S may be increased. However, as the use of dielectric materials of high dielectric constant is limited to certain materials, and as there is also a limit to the extent to which the distance d between the electrodes can be reduced, the chosen method is usually to increase the surface area S of the capacitor.
However, attempts to increase the surface area S of the capacitor led to an increase of chip surface area, and this directly results in higher unit costs for chips.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a semiconductor device having a high capacitance capacitor having a small surface area, to provide a method of efficiently fabricating such a semiconductor device, and to provide a sputtering apparatus suitable for this fabrication method.
According to one aspect of the present invention, a method of fabricating a semiconductor device comprises the steps of: (a) forming a mask layer over an upper surface of a semiconductor substrate such that the mask layer has an aperture penetrating the mask layer and having an inclined lateral wall so as to make the aperture inverted taper shaped; (b) forming a first dielectric layer at a first area over the upper surface of the semiconductor substrate within the aperture by sputtering at a first sputtering incidence direction; and (c) forming a first electrode layer at a second area over the upper surface of the semiconductor substrate within the aperture by sputtering at a second sputtering incidence direction which is different from the first sputtering incidence direction.
This method may further comprises the steps of: (f) forming a second dielectric layer at a third area over the upper surface of the semiconductor substrate within the aperture by sputtering at a third sputtering incidence direction; and (g) forming a third electrode layer at a fourth area over the upper surface of the semiconductor substrate within the aperture by sputtering at a fourth sputtering incidence direction which is different from the first to third sputtering incidence directions.
Further, in this method, the steps (b), (c), (f) and (g) may be repeated in this order at desired times.
According to another aspect of the present invention, a semiconductor device wherein a capacitor is formed on a chemical compound semiconductor substrate, wherein the capacitor comprises: a first electrode layer; a dielectric layer formed on the first electrode layer; and a second electrode layer formed on the dielectric layer.
According to further aspect of the present invention, a sputtering apparatus comprises: a sputtering chamber; a wafer stage on which a wafer is set; and a target stage on which a sputtering material is set. The wafer stage and the target stage is installed in the sputtering chamber. The wafer stage comprises: a fixed stage fixed to the sputtering chamber; and a movable wafer holder holding the wafer and being free to rotate on the fixed stage, thereby making a sputtering incidence direction a desired direction.
According to still further aspect of the present invention, a sputtering apparatus comprises: a sputtering chamber; a wafer stage on which a wafer is set; and a plurality of target stages on which a sputtering material is set respectively. The wafer stage and the target stages is installed in the sputtering chamber, and the target stages is disposed in positions at which sputtering incidence directions with respect to an upper surface of the wafer are mutually different. A sputtering material set on one of the target stages is deposited over the wafer by applying a high frequency voltage between the wafer stage and the one of the target stage, thereby depositing the sputtering material over the upper surface of the wafer.
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Nishiitsuji et al., “A new GaAs MMIC process technology using 0.5&mgr;m gate asymmetric LLDD structure GaAs BP-MESFETs combined with high-dielectric-constant thin-film capacitors,” Semiconductor Science and Technology, vol. 10, No. 11, Nov. 1, 1995, pp. 1534-1540.
“Gallium Arsenide Processing Techniques,” published in 1984 by Artech House Inc., pp. 306-314.
Frank Robert J.
Kennedy Jennifer M.
Niebling John F.
OKI Electric Industry Co., Ltd.
Sartori Michael A.
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