Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-10-13
2001-09-18
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S398000
Reexamination Certificate
active
06291294
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a method for manufacturing dynamic random access memory (DRAM), and more specifically, to a method for manufacturing a stack capacitor using amorphous polysilicon and HSG polysilicon.
BACKGROUND OF THE INVENTION
It has been the trend to scale down the sizes of memory cells to increase the integration level and thus memory capacity of a DRAM chip. As the size of DRAMs is decreased, the capacity of the capacitor used in the DRAM is correspondingly decreased.
A memory cell of DRAM typically consists of a storage capacitor and an access transistor. With the advent of large-scale integrated DRAM devices, the size of the devices has gotten smaller and smaller such that the available area for a single memory cell has become very small. This causes a reduction in the capacitor's area, resulting in the reduction of the cell's capacitance.
One method for increasing capacitance area involves forming hemispherical grain (HSG) polysilicon on amorphous polysilicon and increasing capacitor height. However, increasing capacitor height requires an increase in the amorphous polysilicon layer which requires an increased deposition time for the amorphous polysilicon layer. An increased deposition time causes crystallization of the amorphous polysilicon. Crystallization of the amorphous polysilicon inhibits silicon migration resulting in poor HSG formation atop the amorphous polysilicon. For amorphous silicon deposition, mono-silane (SiH
4
) is the reactant gas most frequently used. Although using di-silane (Si
2
H
6
) reduces the deposition time, changing existing equipment required is costly.
Therefore, there is a need for an improved method for manufacturing a stack capacitor that reduces crystallization of the amorphous polysilicon and that can be used with existing equipment.
SUMMARY OF THE INVENTION
A method for manufacturing a bottom storage node of a stack capacitor on a substrate is disclosed. The method comprises the steps of: (1) forming a first dielectric layer onto said substrate; (2) forming a nitride layer onto said first dielectric layer; (3) patterning and etching said first dielectric layer and said nitride layer until said substrate is reached, to form a contact opening; (4) forming a first conducting layer into said contact opening and atop said nitride layer; (5) removing a portion of said first conducting layer atop said first dielectric layer to form a plug in said contact opening; (6) forming a second dielectric layer atop said nitride layer and said plug; (7) patterning and etching said second dielectric layer to form a trench above said plug; (8) forming an amorphous polysilicon layer into said trench and atop said second dielectric layer; (9) removing a portion of said amorphous polysilicon layer atop said second dielectric layer; (10) removing remaining portion of said second dielectric layer; and (11) forming an HSG polysilicon layer atop said amorphous polysilicon layer.
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Blakely , Sokoloff, Taylor & Zafman LLP
Dang Trung
Kebede Brook
Taiwan Semiconductor Manufacturing Corporation
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