Active solid-state devices (e.g. – transistors – solid-state diode – Combined with electrical contact or lead – Of specified configuration
Reexamination Certificate
1999-06-25
2001-05-08
Lee, Eddie C. (Department: 2815)
Active solid-state devices (e.g., transistors, solid-state diode
Combined with electrical contact or lead
Of specified configuration
C257S774000, C257S763000, C257S764000
Reexamination Certificate
active
06229214
ABSTRACT:
This application relies for priority upon Korean Patent Application No. 98-25173, filed on Jun. 29, 1999, the contents of which are herein incorporated by reference in their entirety.
Field of the Invention
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for fabricating a contact electrode.
Background of the Invention
As DRAM (dynamic random access memory) devices are continuously scaled down, bit lines on these devices are increasingly made of a metal to improve their quality and to reduce chip size. However, metal bit lines are lower in sheet resistance than conventional bit lines overlaid in polysilicon and WSi
x
.
Accordingly, if an equal sheet resistance is required, a pattern of a bit line made of the metal may be more delicate than a conventional pattern. Furthermore, the resistance of a contact formed on an N-type impurity area may be lower than that of a conventional contact, and a contact may be also formed on a P-type impurity area.
FIG. 1
illustrates a conventional semiconductor device, and
FIGS. 2A through 2B
illustrate the distribution of the contact resistance according to the size of a contact on each impurity area (annealed at 750° C., for 100 min).
Referring to
FIG. 1
, an N-type well
11
and a P-type well
12
are respectively formed in a semiconductor substrate
10
with a well formation mask (not shown). Afterwards, a P
+
-type impurity area
13
is formed in the N-type well
11
with an impurity area formation mask (not shown), and an N
+
-type impurity area
14
is formed in the P-type well with the impurity area formation mask.
Boron (B) is implanted into the P
+
-type impurity area
13
, and either arsenic (As) or phosphorous (P) is implanted into the P
+
-type impurity area
14
.
An oxide layer
16
, used as an insulating layer, is formed over the semiconductor substrate
10
. The oxide layer
16
is etched with a contact formation mask (not shown) until portions of the N
+
-type impurity area
13
and the P
+
-type impurity area
14
are respectively exposed, and so that a contact hole
17
is formed. The contact hole
17
has an equal width W over both the P
+
-type impurity area
13
and the N
+
-type impurity area
14
. Afterwards, a metal wire
18
is formed by filling the contact hole
17
with a metal material.
Several methods of forming a metal wire
18
are possible. In one method for forming the metal wire
18
, a Ti layer (not shown) is formed on both sidewalls and on a bottom surface of the contact hole
17
as well as over the oxide layer
16
. Afterwards, the Ti reacts with silicon (Si) in the semiconductor substrate
10
through an annealing process, so that a TiSi
x
layer (that is, an ohmic layer) is formed. After the removal of the remainder of the Ti layer that did not react with the semiconductor substrate
10
from both sidewalls of the contact hole
17
and from the oxide layer
16
, the contact hole
17
is filled with TiN or TiN/W, so that a metal wire is formed.
Using another possible method, a Ti layer and a TiN layer are sequentially deposited on both sidewalls of the contact hole
17
, a bottom area, and the oxide layer
16
. Then, an annealing process is performed to form an ohmic layer. Afterwards, the contact hole is filled with tungsten (W), so that a metal wire is formed.
Using yet another method, a Ti layer and a TiN layer are sequentially deposited on both sidewalls of the contact hole
17
, a bottom area, and the oxide layer
16
. Then, tungsten (W) is directly deposited to form a metal wire. Afterwards, the Ti reacts with the Si of the semiconductor substrate
10
through a later annealing process, so that an ohmic layer is formed.
In the case where a TiSi
x
layer is used as an ohmic layer, boron (B) ions that are doped in the P
+
-type impurity area
13
and the TiSi
x
layer are reacted through a later annealing process, so that a TiB layer is formed.
Since TiB is nonconductive, however, the contact resistance increases. Also, as the doping concentration is lowered due to drain of B ions, the resistance increases. In order to reduce the surface area energy, the TiSi
x
layer is then agglomerated, so that an effective connecting area is reduced to increase the resistance. Arsenic (As) or phosphorous (P) doped on the N
+
-type impurity area do not react with the Ti of the TiSi
x
layer.
As shown in
FIGS. 2A through 2B
, when a contact size is more than about 0.3 &mgr;m in diameter, the contact resistance of an N-type impurity area is less than about 300 &OHgr;/CNT (ohms per contact) and that of a P-type impurity area is about less than 800 &OHgr;/CNT.
On the other hand, when the contact size is reduced to be about 0.15 &mgr;m in diameter, the contact resistance increases more quickly in the P
+
-type impurity area
13
than in the N
+
-type impurity area
14
, as shown in
FIGS. 2A through 2B
.
If the contact resistance generated in the P-type impurity area need not be more than 5,000 &OHgr;/CNT for a given device design, then a chip size should increase so as to reduce the contact resistance. It is, therefore, essential to realize a technique of restraining this phenomenon.
SUMMARY OF THE INVENTION
It is a key feature of the present invention to provide a method for reducing the contact resistance generated on a P-type impurity area without increasing the chip size.
According to the present invention, the method comprises forming a first conductive well in a semiconductor substrate, forming a second conductive well in the semiconductor substrate, forming a first impurity area in the first conductive well, forming a second impurity area in the second conductive well, forming an insulating layer over the semiconductor substrate, and etching the insulating layer by using a contact hole formation mask until a portion of the first and second impurity areas are exposed, thereby forming a first contact hole and a second contact hole, respectively.
A first width of the first contact hole is preferably larger than a second width of the second contact hole. More specifically, the first width of the first contact hole is preferably at least 10% larger than the second width of the second contact hole.
The first conductive well is preferably an N-type well and the second conductive well is preferably a P-type well. Alternatively, the first impurity area may be a P-type area and the second impurity area may be an N-type area. In this latter case, the first contact hole formed over the first impurity area is preferably increased in its dimension by an amount corresponding to a decrease in the dimension of the second contact hole. The smallest contact hole formed over the first impurity area is preferably larger than the smallest contact hole formed over the second impurity area.
According to the present invention, the resulting semiconductor device comprises a semiconductor substrate, a first conductive well formed in the semiconductor substrate, a second conductive well formed in the semiconductor substrate, a first impurity area formed in the first conductive well, a second impurity area formed in the second conductive well, an insulating layer formed over the semiconductor substrate, a first contact hole formed in the insulating layer over the first impurity area, a second contact hole formed in the insulating layer over the second impurity area, a first contact electrode passing through the first contact hole and being electrically connected to the first impurity area, and a second contact electrode passing through the second contact hole and being electrically connected to the second impurity area.
The first width of the first contact hole is preferably larger than a second width of the second contact hole. More specifically, the first width of the first contact hole is preferably at least 10% larger than the second width of the second contact hole.
Alternatively, a method for fabricating a semiconductor device may comprise forming a first conductive well in a semiconductor substrate, formi
Clark Jhihan B
Jones Volentine, L.L.C.
Lee Eddie C.
Samsung Electronics Co,. Ltd.
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