Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-04-14
2001-09-04
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S563000
Reexamination Certificate
active
06284612
ABSTRACT:
CROSS REFERENCE TO RELATED APPLICATIONS
This invention is a continuation application of an application filed the same day under the same title of “PROCESS TO FABRICATE ULTRA-SHORT CHANNEL MOSFETs WITH SELF-ALIGNED SILICIDE CONTACT”, which is a continuation-in-part application of an application filed under the title of “ULTRA-SHORT CHANNEL MOSFETs WITH SELF-ALIGNED SILICIDE CONTACT”, which is a continuation of an application with the Ser. No. of 09/050,670 filed at Mar. 30, 1998, under the same title, wherein all of the applications are assigned to same assignee with the same inventor as the present application.
FIELD OF THE INVENTION
The present invention relates to a semiconductor device, and more specifically, to a method of fabricating a metal oxide semiconductor field effect transistor (MOSFET).
BACKGROUND OF THE INVENTION
Metal oxide semiconductor field effect transistors (MOSFETs) have been traditionally used and widely applied in semiconductor technologies. Device dimensions have been continuously scaled down to achieve high-performance CMOS ULSI (Ultra-Large Scale Integration) devices. For such down-scaled devices, however, parasitics such as RC delay and source/drain series resistance may easily degrade the circuit performance. As suggested in reference by M. T. Takagi, et al., in IEDM Tech. Dig. p.455, 1996, the degration factor of propagation delay on the gate electrode is a relevant function of both channel width and gate electrode sheet resistance. Thus, the finite value of gate electrode sheet resistance limits the maximum channel width of which can be used in ULSIs.
Self-Aligned Ti Silicide contact source/drain and gate (Ti salicide) process is one of the candidates for low gate electrode sheet resistance and low source/drain resistance. The ultra-short channel MOSFET with self-aligned silicide contact is required for high-speed circuit. However, as mentioned in the reference by M. Ono, et al., in IEDM Tech. Dig., p119, 1993, it is difficult to define the gate length to be below 0.1 &mgr;m due to the limitation of current optical lithography.
SUMMARY OF THE INVENTION
The present invention proposes a simplified process to fabricate ultra-short channel nMOSFET with self-aligned silicide contact for a high-speed device. The processes are described as follows. After growing a thin gate oxide film on a silicon substrate, an undoped poly-Si or amorphous Si (&agr;-Si) film was deposited by LPCVD system. Then, a thin first dielectric layer and a photoresist layer were deposited. The gate region was defined on the photoresist layer. The size of the gate region defined on the photoresist layer is then narrowed by etching the photoresist layer. The dimension could be reduced to a narrower dimension than the capability of conventional lithography process. The residual photoresist layer was used as a mask to etch the first dielectric layer. The residual photoresist layer and the first dielectric layer were used as a mask to etch undoped poly-Si to form an ultra-short channel gate.
Next, a CVD PSG film was deposited and then etched back to form PSG spacers. The first dielectric layer was removed and a noble metal was deposited on the whole wafer surface. The source, drain, and gate were doped by a high dose arsenic or phosphorus implantation through the noble (or refractory) metal. Finally, the two-step RTP annealing process was used to form the self-aligned silicided (salicided) contact of nMOSFETs.
REFERENCES:
patent: 4818715 (1989-04-01), Chao
patent: 4837180 (1989-06-01), Chao
patent: 5930617 (1999-07-01), Wu
patent: 6069044 (2000-05-01), Wu
Booth Richard
Texas Instruments - Acer Incorporated
LandOfFree
Process to fabricate ultra-short channel MOSFETs with... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Process to fabricate ultra-short channel MOSFETs with..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Process to fabricate ultra-short channel MOSFETs with... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2452832