Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-12-08
2001-08-14
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S302000
Reexamination Certificate
active
06274448
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of suppressing junction capacitance of source/drain regions, and more particularly to a method of forming the source/drain regions by double implantation.
2.Description of the Related Art
The functioning speed of a transistor can be speed up by shortening channel length while downsizing the MOS devices. The Lightly Doped Drain (LDD) structure is widely used for solving the problem of abnormal function or even dysfunction of a transistor caused by the Short Channel Effect (SCE) and the Hot Electron Effect (HEE) that occur when the channel length is overly shortened. In the method of forming source/drain regions by only one ion implantation step, arsenic ions are widely used. Because arsenic ions are similar to silicon ions in radius, fewer dislocations will be formed when arsenic ions are doped into a silicon substrate. However, as the doping energy increases, dislocations occur even using arsenic ions as dopants.
FIGS. 1A-1B
are cross-sectional views illustrating the fabrication of a MOS transistor in accordance with the prior art;
As shown in
FIG. 1A
, thermal oxidation is used to form a gate oxide layer
11
on the substrate
10
, followed by subsequent deposition of polysilicon and tungsten silicide, after which a gate
12
is defined. Using the gate
12
as a mask, arsenic ions are implanted into the substrate
10
to form a lightly doped drain. The substrate
10
is then placed in a thermal diffusion oven to form the lightly doped regions
16
.
As shown in
FIG. 1B
, silicon dioxide is deposited by chemical vapor deposition (CVD) to cover the substrate
10
and the gate
12
. Portions of the silicon dioxide layer are then etched back to form spacers
14
on the sidewalls of the gate
12
.
Referring to
FIG. 1C
, arsenic ions are heavily and deeply implanted into the substrate while using the gate
12
and the spacers
14
as a mask. The wafer is then annealed to form source/drain regions
18
. Typically, the source/drain regions
18
have a different conductive type from conductive type of the substrate
10
. As the source/drain regions
18
are formed in contact with the substrate
10
, a P-N junction is formed. At P-N junction, holes from P-side diffuse into the N-side, while electrons from N-side diffuse into the P-side. As a consequence, an internal field is built, and a depletion region is formed. The depletion region is electrically neutral. The depletion region plays a role as a dielectric layer within two electrodes, and this structure causes the junction capacitance.
The junction capacitance depends on the width of depletion regions, and the width of depletion regions is related to the junction profile of the implanted ions in the substrate. Because of the abrupt junction profile of arsenic ions, the width of the depletion region is narrow, and the junction capacitance become large. In other words, the high-energy implanted arsenic ions create defects in the silicon crystal structure of the substrate and this causes some leakage in the source/drain regions
18
.
SUMMARY OF THE INVENTION
It is therefore an object of the invention to provide an improved method of suppressing the junction capacitance in the source/drain regions. A lightly and deeply phosphorus ions implantation followed by another arsenic implantation to the source/drain regions is performed to suppress the junction profile of arsenic ions between the source/drain regions and the well. The suppression of the junction profile of arsenic ions increases the width of the depletion regions, reduces the junction capacitance, and in this manner increases the functioning speed of semiconductor devices. Further more, phosphorus ion implantation lower the energy needed in the arsenic ion implantation and reduces the defects formed in the substrate surface by ion bombardments.
To achieve these objects and advantages, and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention is directed towards a method of suppressing junction capacitance of the source/drain regions. First, a gate oxide layer is formed on a substrate, followed by formation of a polysilicon layer on the gate oxide layer, after which the gate structure is defined. With the gate as a mask, low-dosage arsenic ions are implanted into the substrate to form the lightly doped regions. An insulating layer is deposited over the substrate and covers the gate, after which portions of the insulating layer are dry etched to form spacers on the sidewalls of the gate. Phosphorus ions are implanted into the substrate using the gate and spacers as a mask, and then the other ion implantation with arsenic ions is performed. The doped arsenic and phosphorus ions reach uniform distributions in the source/drain regions by a thermal process, and fabrication of the transistor is finished.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
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patent: 4956311 (1990-09-01), Liou et al.
patent: 4963504 (1990-10-01), Huang
patent: 5015595 (1991-05-01), Wollesen
patent: 5100815 (1992-03-01), Tsubone et al.
patent: 5340760 (1994-08-01), Komori et al.
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patent: 5888861 (1999-03-01), Chien et al.
Chou Jih-Wen
Lin Tony
Yeh Wen-Kuan
Lindsay Jr. Walter L.
Niebling John F.
United Microelectronics Corp.
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