Static information storage and retrieval – Systems using particular element – Flip-flop
Reexamination Certificate
1999-07-26
2001-06-05
Dinh, Son T. (Department: 2824)
Static information storage and retrieval
Systems using particular element
Flip-flop
C257S903000
Reexamination Certificate
active
06243286
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, in particular, an SRAM and a method of fabricating the same.
2. Description of the Related Art
FIG. 32
is a plan view showing a memory cell of a conventional SRAM disclosed in Japanese Patent Application Laid-Open No. 45796/1997. Active regions
112
a
,
112
b
,
112
c
, and
112
d
are formed on the main surface of a silicon substrate
111
. Source and drain regions in the active regions
112
a
and
112
b
are n-type and source and drain regions in the active regions
112
c
and
112
d
are p-type. These active regions
112
a
,
112
b
,
112
c
, and
112
d
are isolated from each other by a field oxide region
113
.
A first conductive layer
116
a
extends from an area on the active region
112
c
to an area on the active region
112
a
. The first conductive layer
116
a
is a gate electrode for a load transistor Q
6
and a driver transistor Q
4
.
A second conductive layer
116
b
branches from the first conductive layer
116
a
on the field oxide region
113
and extends toward an area on the active region
112
b.
A third conductive layer
116
c
passes across the active region
112
b
and the active region
112
d
, bends on the field oxide region
113
, and extends toward an area on the active region
112
c
. The third conductive layer
116
c
is a gate electrode for a load transistor Q
5
and a driver transistor Q
3
. Note that access transistors Q
1
and Q
2
are not shown in this figure.
FIG. 33
is a cross section of the memory cell of the SRAM along the A—A line. A p-type well
110
a
and an n-type well
110
b
are formed on the silicon substrate
111
. The active region
112
a
is formed on the p-type well
110
a
, and the active region
112
c
is formed on the n-type well
110
b
. The active region
112
a
is isolated from the active region
112
c
by the field oxide region
113
.
The second conductive layer
116
b
is formed on the field oxide region
113
. Side wall insulating films
117
are formed on the sides of the second conductive layer
116
b.
The conventional SRAM shown in
FIG. 32
has two problems. First problem will be described below.
The SRAM shown in
FIG. 32
is formed by laminating a conductive layer and an insulating layer on the main surface of the silicon substrate
111
. A mask alignment is indispensable in this lamination step. A mask alignment error may occur in such a mask alignment.
FIG. 34
is a plan view of a memory cell showing a mask alignment error caused by a mask shifted in the direction of the Y axis at the time of forming the first conductive layer
116
a
, the second conductive layer
116
b
, and the third conductive layer
116
c
.
FIG. 35
is a cross section of the memory cell of the SRAM shown in
FIG. 34
along the A—A line.
In
FIGS. 34 and 35
, part of the second conductive layer
116
b
and the side wall insulating film
117
overlap the region designed to be the active region
112
a
. Because of this, the gate width of the gate electrode of the driver transistor Q
4
is W in the plan but actually is w, which is smaller than W. This causes an imbalance in the &bgr; ratio (capacity ratio of driver transistor to transfer transistor), causing the characteristics of the SRAM to deteriorate.
It is therefore necessary to take the mask alignment error into account when designing the layout of the SRAM. As shown in
FIG. 33
, the width of the field oxide region
113
must be wide enough to allow the second conductive layer
116
b
and the side wall insulating film
117
to be located on the field oxide region
113
, even if the mask alignment error occurs. However, this goes against the need for a reduced memory cell size.
Second problem is as follows.
FIG. 36
shows an end section of the active region
112
c
shown in FIG.
32
. In the plan, the active region
112
c
is designed to be within a solid line
119
, but actually, the active region
112
c
is formed within a broken line
120
due to a bird's beak
118
. Since the active region is narrow in the end section of the active region
112
c
and oxidized from three directions in a LOCOS process, the effective active region is small as shown in FIG.
36
. The active region
112
c
is in contact with an upper wiring layer. If the area of the active region
112
c
is small, the margin is reduced when the active region
112
c
is connected to the wiring in the upper layer.
SUMMARY OF THE INVENTION
The present invention has been achieved to solve the above problems. An object of the present invention is to provide a semiconductor memory device in which a memory cell can be miniaturized without causing an imbalance in the &bgr; ratio of the memory cell, and a method of fabricating the semiconductor device.
The present invention has, in addition to the above object, an object of providing a semiconductor memory device well contacted with the upper wiring layer and a method of fabricating such semiconductor memory device.
According a first aspect of the present invention, there is provided a semiconductor memory device having at least one memory cell that includes first and second load transistors and first and second driver transistors, the semiconductor memory device comprising:
a semiconductor substrate having a main surface;
a first load transistor active region which is formed on the main surface as an active region for the first load transistor;
a second load transistor active region which is formed on the main surface as an active region for the second load transistor;
a first driver transistor active region which is formed on the main surface as an active region for the first driver transistor;
a second driver transistor active region which is formed on the main surface as an active region for the second driver transistor;
a first element isolation region which is formed on the main surface to isolate the first load transistor active region from the first driver transistor active region;
a first conductive layer which extends from an area on the first load transistor active region to an area on the first driver transistor active region to be a gate electrode for the first load transistor and for the first driver transistor;
a second conductive layer which branches from the first conductive layer on the first element isolation region and is electrically connected to the second driver transistor active region, wherein the width of part of the second conductive layer positioned on the first element isolation region is less than the width of the first conductive layer; and
a third conductive layer which is electrically connected to the first load transistor active region, passes across the second load transistor active region, and extends toward an area on the second driver transistor active region to be a gate electrode for the second load transistor and the second driver transistor.
In the semiconductor memory device according to the present invention, the width of part of the second conductive layer on the first element isolation region is smaller than the width of the first conductive layer. Hence the width of the second conductive layer on the first element isolation region can be less in comparison with the case where the width of the second conductive layer on the first element isolation region is the same as or larger than the width of the first conductive layer. So the width of the first element isolation region can also be less even if a mask alignment error is taken into account when forming the first through third conductive layers. Therefore, a memory cell can be miniaturized without causing an imbalance in the &bgr; ratio of the memory cell.
According to a second aspect of the present invention, there is provided a semiconductor memory device having at least one memory cell that includes first and second load transistors and first and second driver transistors, the semiconductor memory device comprising:
a semiconductor substrate having a main surface;
a first load transistor active region which is formed on the main surface as an active reg
Karasawa Junichi
Kumagai Takashi
Tanaka Kazuo
Watanabe Kunio
Dinh Son T.
Hogan & Hartson LLP
Seiko Epson Corporation
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