Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
1998-07-27
2001-08-07
Loke, Steven (Department: 2811)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S408000, C257S410000
Reexamination Certificate
active
06271563
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a MOS transistor with a high-K spacer designed for ultra-large-scale integration, and, more particularly, to a MOS transistor having shallow source/drain extension regions to minimize short-channel effects.
2. Description of Related Art
Attempts continue to shrink the dimensions of MOS transistors. Devices having sub-micrometer dimensions permit closer placement of devices thereby increasing the density of devices on a chip and their operating speed.
As the size of MOS transistors decreases, the distance between the source and drain wells of a transistor, i.e., channel length, also decreases thereby subjecting the transistor to what is called “the short-channel effect.” As the effective channel length of a transistor shrinks below about 0.10 micron, electrical effects begin to reduce the threshold voltage and increase leakage current of the device which eventually make the transducer useless.
One approach to minimizing the short-channel effect has been to make the depth of the channel between the source and drain shallow relative to its length. Generally this is done in one of two ways. One way is to raise the source and drain above the surface of the silicon substrate. Another way is to create extensions of the source and drain wells that are shallower in depth than the source and drain wells. These shallow extensions allow the formation of a channel between the extensions that is shallower than would otherwise occur. One way to create shallower drain and source extensions is by ion implantation.
Creating shallow drain and source extension regions by ion implantation is very difficult. At conventional implantation energy, those ions are driven deep into the silicon thereby forming a deep channel. If the implantation energy is reduced to keep the implant shallow, the individual ions' electrical fields repel one another thereby scattering and diffusing the implant which is undesirable.
Another approach has been to use cluster ion-beam implantation. At the Kyoto University in Japan, it was reported that a beam of B
10
H
14
ions were implanted at 2 KeV with a dose of 10
12
ions/cm
2
. It was reported that by using cluster ion-beam implantation, a shallower channel resulted. It was reported that cluster ion-implantation created a functioning p-channel MOS transistor with a 40 nanometer gate, however, the device showed some threshold degradation as a result of the short-channel effect. A 50 nanometer transistor was reportedly built using the same technique and exhibited reportedly good gain and 0.4 mA/micron current.
In order to minimize or eliminate short-channel effects of devices created for ultra-large-scale-integration, it is desirable to provide a MOS transistor having the depth of the channel region shallower than 40 nanometer.
It is thus desirable to provide a transistor that provides acceptable immunity to short-channel effects that can be utilized in ultra-large-scale integration. It is also desirable to provide a method for fabricating such a transistor. Furthermore, it is desirable to provide a transistor that has a source/drain extension depth of less than 40 nanometers.
SUMMARY OF THE INVENTION
Advantages of the present invention will become apparent upon consideration of the following detailed description of the presently preferred embodiments of the invention together with the accompanying drawings.
According to one aspect of the invention, there is provided a MOS transistor comprising a source well located in a substrate, a drain well located in the substrate, a channel located in the substrate between the source and drain wells wherein the channel separates the source and drain wells, a source extension located in a portion of the channel adjacent to and coupled with the source well wherein the source extension has a thickness less than 40 nanometers, a drain extension located in a portion of the channel adjacent to and coupled with the drain well wherein the drain extension has a thickness less than 40 nanometers, and a gate disposed on the surface of the substrate located over the channel.
According to a second aspect of the invention, there is provided a method of making a MOS transistor, the method comprising the steps of forming a gate stack on a surface of a substrate, forming an oxide spacer on sides of the gate stack, depositing a layer of high-K dielectric material over the gate stack and the surface of the substrate, reducing the thickness of the layer of high-K dielectric material to less than the thickness of the gate stack to expose a portion of the gate electrode material such as polysilicon, removing the exposed portion of the high-K dielectric and oxide spacer, depositing polysilicon over the gate stack and the layer of high-K dielectric material, removing a portion of the polysilicon to form a T-shape gate and removing a portion of the high-K dielectric material outside of the gate.
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patent: 4994869 (1991-02-01), Matloubian et al.
patent: 5091324 (1992-02-01), Hsu et al.
patent: 5215937 (1993-06-01), Erb et al.
patent: 5243212 (1993-09-01), Williams
patent: 5347153 (1994-09-01), Bakeman, Jr.
patent: 5554876 (1996-09-01), Kusunoki et al.
patent: 5661059 (1997-08-01), Liu et al.
patent: 5698883 (1997-12-01), Mizuno
Hara, Yoshiko, “Japan Sees Shortcut to 0.05-Micron Chip,”EE Times—Headline News(1998), pp. 1-3.
Wolf, Stanley, “Silicon Processing for the VLSI ERA.” vol. 3:The Submicron MOSFET, pp. 136-138.
Lin Ming-Ren
Yu Bin
Advanced Micro Devices , Inc.
Eschweiler & Associates LLC
Loke Steven
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