Semiconductor device manufacturing: process – Coating with electrically or thermally conductive material – To form ohmic contact to semiconductive material
Reexamination Certificate
1998-03-05
2001-05-08
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Coating with electrically or thermally conductive material
To form ohmic contact to semiconductive material
C438S625000, C438S636000, C438S637000, C438S643000, C438S669000, C438S627000
Reexamination Certificate
active
06228757
ABSTRACT:
FIELD OF THE INVENTION
The present invention is, in general, directed to a process for making a semiconductor device. In particular, the present invention relates to a process for making a semiconductor device having overlapping interconnects, in which the production of recesses in the interconnects is prevented or reduced.
BACKGROUND OF THE INVENTION
Over the last few decades, the electronics industry has developed semiconductor technology to fabricate small, highly integrated electronic devices. Many semiconductor devices are now formed by vertical stacking of device layers, including multiple layers of conductive lines with interconnects between layers. As these devices become smaller, there is a need for increasingly narrow conductive lines and interconnects to form circuit pathways within these devices. These conductive lines and interconnects are typically formed using metals, including, for example, aluminum, tungsten, and copper.
In a multilevel architecture, layers of metal conductive lines which define circuit pathways are separated from each other by interlevel dielectrics. In a typical process scheme, a first metal layer is deposited and patterned to form a first set of conductive lines. This is followed by deposition of a dielectric layer over the first set of conductive lines. Vias are etched through the dielectric layer to the underlying conductive lines and then filled with metal to establish interlayer conduction. In conventional processing methods, the metal which fills the vias typically extends beyond the via when deposited. This excess metal is removed by, for example, chemical-mechanical polishing or etch back. A second metal layer may then be formed over the dielectric layer and patterned into a second set conductive lines.
With current aggressive design rules, it is not always possible to have complete overlap of conductive lines with underlying vias. This typically leaves at least a portion of the vias exposed during the etch process in which second set of conductive lines are patterned. A recess in the exposed portion of the vias may be formed during this process. For example, if an aluminum conductive line is formed over the via and the aluminum conductive line does not completely overlap the underlying via, then there is a possibility that a portion of the via may be etched during the formation of the conductive lines, which typically includes one or more metal etching steps.
Tungsten is used to fill the vias in order to reduce the amount of recessing during subsequent processing steps. Tungsten-filled vias provide adequate selectivity during metal etching steps. However, the presence of tungsten in the path of current flow may lead to flux divergence in the metal lines at the tungsten/metal interfaces resulting in the degradation of the electromigration resistance.
To address this issue, aluminum and aluminum alloys have been suggested for incorporation in the vias. In addition to reducing via resistance, aluminum vias may also show better electromigration resistance. The use of aluminum in vias is expected to become more important as the device dimensions become smaller. Conventional techniques include filling the vias with tungsten or aluminum, polishing or etching back the tungsten or aluminum to remove excess deposits outside of the via, and then depositing a second metal layer for making the conductive lines.
When aluminum is incorporated in the vias, a conventional metal etch technique cannot be used to form the conductive lines, which are also typically aluminum, because the aluminum in the vias may be exposed to metal etchants which may create recessing in the vias. This recessing can lead to electromigration failure. Furthermore, recesses in the vias may trap chemicals or gases during subsequent processing steps. These chemicals and gases may lead to device degradation over time. In addition, the effective thinning of the via due to the presence of the recess increases the current density through that portion of the via which may lead to local overheating and electromigration. Thus, there is a need for an improved method for forming vias and conductive lines in a semiconductor device to prevent the formation of recesses in non-overlapping portions of the via during processing.
SUMMARY OF THE INVENTION
Generally, the present invention relates to a process for manufacturing a semiconductor device having metal interconnects. The process reduces or eliminates the recessing of metal in the vias, particularly when the vias are formed using aluminum or an aluminum alloy. One embodiment is a method for producing a semiconductor device. A via is formed in a device layer of the semiconductor device. A barrier layer is formed over the device layer. A metal layer is formed over the barrier layer and also fills the via to form a via structure. A portion of the metal layer is removed and a remaining portion of the metal layer forms a conductive structure having a sidewall extending from a surface of the barrier layer. A spacer is then formed along the sidewall of the conductive structure and a portion of the barrier layer is removed using the spacer to protect a portion of the via structure adjacent the surface of the device layer.
Another embodiment is a method for producing a semiconductor device. A via is etched in a dielectric layer of the semiconductor device. The via has a sidewall and a bottom surface. A barrier layer is deposited on the surface of the dielectric layer and on the sidewall and the bottom surface of the via. A metal layer is formed over the barrier layer and fills the via to form a via structure. An anti-reflective coating (ARC) layer is formed over the metal layer and a photoresist layer is formed over the anti-reflective coating layer. A pattern is formed in the photoresist layer and portions of the anti-reflective coating layer and the metal layer are removed to expose the barrier layer according to the pattern. A remainder of the anti-reflective coating layer and the metal layer form a conductive structure having a sidewall extending from a top surface of the barrier layer. The conductive structure and the barrier layer are covered with a spacer material which is then etched to expose the barrier layer. A remainder of the spacer material forms a spacer on the sidewall of the conductive structure. A portion of the barrier layer adjacent to at least one of the conductive structure and the via structure is then removed with the spacer protecting the via structure adjacent the surface of the device layer.
A further embodiment is a semiconductor device made using the methods described above.
Yet another embodiment is a semiconductor device. The semiconductor device has a device layer and a via in the device layer. Metallic material is disposed in the via. A conductive structure is formed over the via and in contact with the metallic material. The conductive structure has a sidewall extending form the device layer. During processing the metallic material in the via is protected by a spacer formed on the sidewall of the conductive structure during the removal of a portion of a conducting barrier adjacent the via and over the device layer.
The above summary of the present invention is not intended to describe each disclosed embodiment or every implementation of the present invention. The Figures and the detailed description which follow more particularly exemplify these embodiments.
REFERENCES:
patent: 5242861 (1993-09-01), Inaba
patent: 5656543 (1997-08-01), Chung
patent: 5877082 (1999-03-01), Kimizuka et al.
Sengupta Samit
Zheng Tammy
Bowers Charles
Pham Thanhha
Philips Semiconductors Inc.
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