Method for forming self-aligned contact

Details Method for forming self-aligned contact Method for forming self-aligned contact

1999-07-30

2001-03-06

Wong, Don (Department: 2821)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S597000, C438S618000, C438S624000, C438S637000, 43

Reexamination Certificate

active

06197670

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method for fabricating a semiconductor device, and more particularly to a method for forming a self-aligned contact of a DRAM (dynamic random access memory).
BACKGROUND OF THE INVENTION
The high integration of a DRAM (dynamic random access memory) device leads to a decrease of the cell pitch size. It is therefore important to insure misalignment margin in a fabricating process of a Gigabit DRAM and less.
Owing to the limitation of photolithography and etching techniques, it is the most important and difficult to insure misalignment margin of a storage node contact to a gate electrode, a bit line, and a storage node during formation of a cell.
Referring to
FIG. 1A
, by forming a shallow trench isolation
12
on a semiconductor substrate
10
, an active region and an inactive region are defined. A conductive layer (that is, gate electrode) is formed on the active region. The gate electrode has a structure that a silicide layer is layered on a polysilicon layer. A top surface and both sidewalls of the gate electrode are covered with a nitride layer spacer. A first oxide layer
14
as an insulating layer is formed to cover up the semiconductor substrate
10
including the trench isolation
12
.
Then, a self-aligned contact (referring to below as SAC) process is performed. That is, using a contact hole formation mask, the first oxide layer
14
on the active region is etched to form a pad formation contact hole. After filling the contact hole with a polysilicon layer, the polysilicon layer is planarized to be coplanar with the first oxide layer
14
through a CMP (chemical mechanical polishing) process. As a result, a storage node contact pad
16
which is electrically connected to the semiconductor substrate
10
is formed. Simultaneously is formed a bit line contact pad (not shown) connecting a bit line to the semiconductor substrate
10
in a following process.
Referring to
FIG. 1B
, a second oxide layer
18
is formed on the first oxide layer
14
including the storage node contact pad
16
. The second oxide layer is made of, for example, P-TEOS (plasma-tetraethylorthosilicate) with a thickness of about 1,000 Å. Using a contact hole formation mask, the second oxide layer
18
is etched to form a bit line contact hole (not shown).
A bit line
20
which is electrically connected to the bit line contact pad via the bit line contact hole is formed. A third oxide layer
22
, a nitride layer
24
, and a fourth oxide layer
26
are sequentially formed on the second oxide layer
18
including the bit line
20
. When a capacitor dielectric film is formed in the following process, O
2
is created to oxidize the bit line
20
. The nitride layer
24
may suppress the oxidation of the bit line
20
. The total thickness of the second oxide layer
18
, the third oxide layer
22
, the nitride layer
24
, and the fourth oxide layer
26
is about 6,000 Å.
Referring to
FIG. 1C
, the fourth oxide layer
26
, the nitride layer
24
, the third oxide layer
22
, and the second oxide layer
18
are sequentially etched down to a top surface of the storage node contact pad
16
by using a contact hole formation mask. Thus, a storage node contact hole
27
is formed. If the mask is misaligned, it is possible to generate a short between the bit line and a storage node contact formed in the following process.
Referring to
FIG. 1D
, a storage node formation conductive layer is formed on the fourth oxide layer
26
including the foregoing storage node contact hole
27
as high as the height of a storage node. Using a storage node formation mask, the conductive layer is patterned to form a storage node
30
which is electrically connected to the storage node contact pad
16
.
When the second oxide layer
18
is etched to form the bit line contact hole, the etching thickness of the oxide layer is relatively thin (about 1,000 Å) and as soon as a contact pad is formed, the bit line is formed. Therefore, it is not difficult to align to the contact pad.
However, there can arise some problems associated with alignment between the contact pad and the storage node. For example, it is very difficult to form a buried contact (storage node contact
28
) by etching a thick nitride layer (e.g., about 6,000 Å). Furthermore, when aligning the storage node contact
28
to the underlying corresponding contact pad, various layers such as a gate electrode line, bit line contact, bit line and storage node serve as obstacles and they must be taken into account. As a result, it is very difficult to ensure enough mis-alignment margin (alignment tolerance) exceeding 50 nm.
However, generally mis-alignment margin between the gate electrode and the storage node contact is less than 40 nm and mis-alignment margin between a bit line and storage node contact is less than 40 nm. The 0.15 nm cell pitch requires storage node contact dimension of 100 nm at the top portion and 80 nm at the bottom portion thereof, but the critical dimension of the storage contact is increased due to the fact that layer to be etched is about exceeding 6,000 A and sufficient overetch process is needed. Therefore, the mis-alignment margin between the storage node and storage node contact becomes very narrow, for example, less than 20 nm.
Accordingly, there is a need for a method which can provide a sufficient mis-alignment margin between the storage node contact and the storage node without producing an electrical bridge.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method for forming a self-aligned contact which suppresses formation of shorts generated by the misalignment of a gate electrode, and insuring a misalignment margin for a storage node contact to a storage node.
According to a first embodiment the present invention, a first insulating layer is formed on a semiconductor substrate where a transistor is formed. The first insulating layer is penetrated to form a first self-aligned contact pad electrically connected to the semiconductor substrate. A second insulating layer is formed on the first insulating layer including the first self-aligned contact pad. A conductive architecture is formed on the second insulating layer. The conductive architecture is covered with a material layer having an etch selectivity with respect to the second insulating layer. A third insulating layer is formed on the second insulating layer including the bit line. The third insulating layer and the second insulating layer are sequentially etched down to a top surface of the first self-aligned contact pad, so that a first opening is formed. A second self-aligned contact pad is formed electrically connected to the first self-aligned contact pad via the first opening. A fourth insulating layer is formed on the third insulating layer, including the second self-aligned contact pad. The fourth insulating layer is etched down to a top surface of the second self-aligned contact pad, so that a second opening is formed. Finally, a storage node is formed electrically connected to the second self-aligned contact pad via the second opening.
According to a second embodiment of the present invention, a first insulating layer is formed on a semiconductor substrate where a transistor is formed. The first insulating layer is penetrated to form a first self-aligned contact pad electrically connected to the semiconductor substrate. A second insulating layer is formed on the first insulating layer including the first self-aligned contact pad. A conductive architecture is formed on the second insulating layer. The conductive architecture is covered with a material layer having an etch selectivity with respect to the second insulating layer. A portion of the second insulating layer is etched down to a top surface of the first self-aligned contact pad by using a photoresist pattern as a mask. A second self-aligned contact pad is formed in the exposed portion thereof. A pad formation conductive layer is formed on the overall surface of the semiconductor substrate. The conductive layer

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