Method of fabricating mask ROM

Details Method of fabricating mask ROM Method of fabricating mask ROM

2000-08-21

2001-04-24

Tsai, Jey (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S276000

Reexamination Certificate

active

06221722

ABSTRACT:

This application claims the benefit of Korean application no. P1999-34805 filed on Aug. 21, 1999, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a mask Read Only Memory (ROM), in which a coding step is adjusted for reducing turn-around time.
2. Discussion of the Related Art
Erasure of and writing on a mask ROM, a nonvolatile memory, is, in general, not possible since code ion implantation, i.e., programming, is done in a device fabrication process. Data programming on the mask ROM is done by using NOR contact, NOR type ion implantation, or NAND type ion implantation.
A conventional method of fabricating a mask ROM will be explained with reference to
FIGS. 1 and 2A
through
2
D. Referring to
FIG. 1
, a conventional method of fabricating a mask ROM begins with an initial fabrication step of a general ROM
100
, i.e., bitlines for use as a drain/source and wordlines for use as gates are formed. This initial step
100
starts with forming a plurality of buried bitlines
14
in an N-type semiconductor substrate
11
having a P-type well
12
formed therein and a plurality of wordlines
16
vertical to the buried bitlines
14
. In a ROM code lithography step
101
, according to custom data, a photoresist film
17
for a ROM code mask is coated, patterned, and exposed. In a code ion implantation step
102
, code ions, such as Boron ions, are selectively implanted. In a first deposition step
103
, a Chemical Vapor Deposition (CVD) oxide film
18
is deposited on the wordline
16
. In a second deposition step
104
, a Boron Phosphorous Silicate Glass (BPSG) oxide film
19
is deposited. In a contact lithography step
105
, the BPSG oxide film
19
is removed selectively to form a contact (not shown). In a metal etch step
106
, a metal is deposited on an entire surface, including the contact, and subjected to selective photolithography and etching to form a metal pattern
20
. In a passivation step
107
, a CVD oxide film is deposited on the entire surface, thereby forming a protection film i.e., passivation, (not shown). Pad lithography and etching are conducted in a pad lithography step
108
. An alloy is then formed in an alloy forming step
109
. A wafer yield prediction is made in a yield prediction step
110
, and a wafer level circuit test is conducted in a circuit test step
111
. Since code ions are implanted in a certain region, i.e., a channel region of a cell transistor after the wordlines are formed, the conventional method
112
of fabricating a mask ROM takes approximately two weeks to complete.
Referring to
FIG. 2A
, an N-type semiconductor substrate
11
is lightly doped with P-type impurity ions to form a P-well
12
. Then, a Local Oxidation of Silicon (LOCOS) is used to form a field oxide film
13
on a region of the substrate
11
. Boron ions are implanted in a surface of the P-type well of the substrate
11
excluding the field oxide film
13
for adjusting a threshold voltage between approximately 0.9V and 1.2V.
Referring to
FIG. 2B
, a buried N+ mask (BN+ mask) is used in implanting arsenic ions in the P-type well
12
. Then, the arsenic ions are activated for forming a plurality of bitlines
14
at fixed intervals. A gate oxide film
15
is formed on the substrate
11
and a doped polysilicon is deposited on the gate oxide film
15
. A first photoresist film (not shown) is then coated on the polysilicon layer and subjected to selective patterning by exposure and etching, thereby forming a plurality of wordlines
16
. The buried bitlines
14
and the wordlines
16
are perpendicular to each other.
Referring to
FIG. 2C
, a second photoresist film (not shown) is coated on the wordlines
16
and subjected to patterning using a code mask. A resulting patterned photoresist film
17
and the wordlines
16
are used as masks in implanting code ions, such as boron ions, to pull-up a cell threshold voltage. Thus, data coding of the mask ROM is done by ion implantation of code ions in a channel region of the cell transistor.
As illustrated in
FIG. 2D
, a CVD oxide film
18
and a BPSG film
19
are deposited on the wordlines
16
and subjected to annealing and reflowing. The BPSG film
19
is selectively removed to expose the buried bitlines
14
which serve as a source/drain of the cell transistor, forming a contact (not shown) and thereafter forming a metal pattern
20
. Then, a protection film
21
is formed on the metal pattern
20
.
A disadvantage of the conventional method for fabricating a mask ROM is that a turn-around time on the custom data after coding is prolonged because the code ions are implanted before the metal pattern is formed.
SUMMARY OF THE INVENTION
Accordingly, the claimed invention is directed to a method of fabricating a mask ROM that substantially obviates one or more of the problems due to limitations and disadvantages of the related art. An object of the claimed invention is to provide a method of fabricating a mask ROM that can shorten a turn-around time.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described, a method of fabricating a mask ROM of the claimed invention includes forming a plurality of buried bitlines in an upper surface of a semiconductor substrate at fixed intervals and a plurality of wordlines on the semiconductor substrate perpendicular to the buried bitlines. An interlayer insulating film having a bitline contact hole is formed on an entire first surface of the semiconductor substrate inclusive of the wordlines. A metal pattern in contact with the buried bitlines through the contact hole is formed. A ROM code mask is formed on the metal pattern. The ROM code mask is used to selectively etch the interlayer insulating film, thereby forming a plurality of ROM code ion implantation regions. ROM code ions are implanted in the ROM code ion implantation regions, which form a protection film on an entire second surface of the semiconductor substrate.
In another aspect, the claimed invention for a method of fabricating a mask ROM includes forming a plurality of buried bitlines at fixed intervals in an upper semiconductor surface. A gate insulating film is formed on a semiconductor substrate. A plurality of wordlines is formed on the gate insulating film perpendicular to the buried bitlines. On an entire surface of the semiconductor substrate, inclusive of the wordlines, an interlayer insulating film is formed. The interlayer insulating film is patterned selectively to form a contact hole. A metal layer is formed on an entire first surface of the semiconductor substrate, inclusive of the contact hole, and the metal layer is patterned to form a metal pattern. A photoresist film is deposited on an entire second surface of the semiconductor substrate, inclusive of the metal pattern, and the photoresist film is exposed and developed to form a second photoresist film for a ROM code mask. The interlayer insulating film is etched using the second photoresist film for the ROM code mask as a first mask, which exposes a plurality of ROM code ion implantation regions. The second photoresist film for the ROM code mask is removed, which exposes a ROM code mask layer. Code ions are implanted into the ROM code ion implantation regions by using the ROM code mask layer as a second mask. A protection film is formed on an entire third surface of the semiconductor substrate inclusive of the metal pattern.
It is to be understood that both the foregoing general description and the following detaile

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