Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-08-25
2001-08-21
Smith, Matthew (Department: 2825)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S301000
Reexamination Certificate
active
06277698
ABSTRACT:
TECHNICAL FIELD
The present invention relates to a method of manufacturing high density semiconductor devices having fully doped gate electrodes. The present invention is particularly applicable in manufacturing high density CMOS semiconductor devices having a design rule of about 0.18 microns and under.
BACKGROUND ART
The escalating requirements for high density and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional semiconductor methodology.
In conventional semiconductor methodology illustrated in
FIG. 1
, an initial gate dielectric layer
12
, such as silicon oxide, is formed on semiconductor substrate
10
and a gate electrode layer formed thereon as in conventional practices. The gate electrode layer, typically polycrystalline silicon, is etched in a conventional manner to form gate electrode
14
on underlying gate oxide layer
12
.
Next, an insulating layer is deposited and etched to form sidewall spacers
16
on the side surfaces of gate electrode
14
and underlying dielectric layer
12
adjacent gate electrode
14
side surfaces, as shown in FIG.
2
. In forming sidewall spacers
16
, gate oxide layer
12
is etched, thereby exposing the surface of semiconductor substrate
10
adjacent sidewall spacers
16
. Subsequently, using gate electrode
14
and sidewall spacers
16
as a mask, impurities are ion implanted, as indicated by arrows
20
in FIG.
2
. The ion implantation functions to form source/drain implants
22
and to dope gate electrode
14
.
As device features continually shrink in size, it becomes necessary to decrease the depth of source/drain regions in the semiconductor substrate, i.e., the junction depth. For example, in forming a polycrystalline silicon gate electrode having a width of about 0.25 microns, the junction depth (X
J
) should be no greater than about 800 Å e.g., less than 500 Å. This objective is extremely difficult to achieve, particularly when implanting impurities to dope the gate electrode and form source/drain regions.
For example, a drawback attendant upon employing a single ion implantation step to form source/drain implants
22
and to dope gate electrode
14
is that impurities implanted to form shallow source/drain implants
22
are implanted at a relatively low energy, e.g., about 0.2 KeV to about 50 KeV. The implanted impurities achieve desirably shallow penetration depth into substrate
10
at the expense of shallow penetration into gate electrode
14
. This causes gate depletion, i.e., lack of carriers at gate electrode
14
/gate oxide
12
interface, resulting in decreased capacitance and reduced drive current.
Additionally, as device features continually shrink in size, various circuit structures/parameters become increasingly important. For example, the profile of gate electrode
14
after etching must be substantially rectangular, i.e., the side surfaces being substantially parallel to each other and substantially perpendicular to the upper surface of semiconductor substrate
10
, to ensure optimum transistor performance and reliability. Conventional semiconductor methodology comprises depositing a layer of polycrystalline silicon followed by etching to form gate electrode
14
. However, due to the large grain size of polycrystalline silicon, it is difficult to form a polysilicon gate electrode with a substantially rectangular profile.
Subsequently, ion implantation is conducted to form source/drain regions of a transistor having a targeted channel length. However, since the profile of gate electrode
14
is often non-rectangular and non-uniform, the channel length of the transistor is difficult to control. For example, variations in the gate electrode profile adversely affect the targeted channel length of the transistor, thereby affecting transistor performance. Certain non-uniformities in the profile can also cause performance degradation, e.g., transistor drive current non-uniformities and asymmetry.
SUMMARY OF THE INVENTION
There exists a need for a method of manufacturing a semiconductor device having fully doped gate electrodes.
There is also a need for a method of manufacturing a semiconductor device having a substantially rectangular gate electrode profile.
Additional advantages and other features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from the practice of the present invention. The advantages of the present invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other advantages are achieved in part by a method of manufacturing a semiconductor device. The method includes forming a first dielectric layer on an upper surface of a semiconductor substrate and forming a film on the first dielectric layer. The method also includes patterning and etching the film to form regions having a rectangular profile on the first dielectric layer separated by open regions and depositing a conductive layer on the semiconductor substrate. The method further includes planarizing the conductive layer to form a gate electrode having an upper surface and side surfaces, wherein the side surfaces are substantially parallel to each other and substantially perpendicular to the upper surface of the semiconductor substrate.
Another aspect of the present invention is a method of manufacturing a CMOS semiconductor device comprising an N-channel transistor region and a P-channel transistor region. The method includes forming a first dielectric layer on an upper surface of a semiconductor substrate and forming a film on the first dielectric layer. The method also includes patterning and etching the film to form regions having a rectangular profile on the first dielectric layer separated by open regions and depositing a conductive layer on the semiconductor substrate. The method further includes planarizing the conductive layer to form a first gate electrode of an N-channel transistor and a second gate electrode of a P-channel transistor with each gate electrode having an upper surface and side surfaces, wherein the side surfaces are substantially parallel to each other and substantially perpendicular to the upper surface of the semiconductor substrate.
Other advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description. The embodiments shown and described provide illustration of the best mode contemplated for carrying out the present invention. The invention is capable of modifications in various obvious respects, all without departing from the present invention. Accordingly, the drawings and description are to be regarded as illustrative in nature, and not as restrictive.
REFERENCES:
patent: 5840604 (1998-11-01), Yoo et al.
patent: 5879975 (1999-03-01), Karlsson et al.
Ishida Emi
Ju Dong-Hyuk
Wu David
Advanced Micro Devices , Inc.
Lee Calvin
Smith Matthew
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