Static information storage and retrieval – Read/write circuit – Having particular data buffer or latch
Reexamination Certificate
2000-07-31
2001-06-26
Fears, Terrell W. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Having particular data buffer or latch
C365S230080, C365S185120
Reexamination Certificate
active
06252804
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor integrated circuit comprising a memory cell and a method of controlling the same. In particular, the present invention relates to a semiconductor integrated circuit having a data masking function.
2. Description of the Related Art
With the development of semiconductor manufacturing technologies, semiconductor integrated circuits have been increasing its operating speed. In particular, the operating frequencies of microcomputers and the like have been improving year after year, further increasing the difference with the operating frequencies of semiconductor memories such as a DRAM.
To reduce this difference, high-speed memories including SDRAMs (Synchronous DRAMs), DDR SDRAMS (Double Data Rate Synchronous DRAMs), and FCRAMs (Fast cycle RAMs) have been developed.
FIG. 1
shows an example of a DDR SDRAM (hereinafter, also simply referred to as SDRAM) in which data are input/output in synchronization with rising edges and falling edges of a clock signal. Parenthetically, in the drawings, those signal lines shown by thick lines each comprise a plurality of lines. Some of the circuits connected with the thick lines consist of a plurality of components.
The SDRAM comprises an input/output control unit
1
, a chip control unit
2
, and a plurality of memory core units
3
. If the SDRAM consists of a plurality of banks, a group of the chip control unit
2
and the memory core units
3
are provided for each of the banks.
The input/output control unit
1
comprises a clock buffer
4
, a command decoder
5
, an address buffer
6
, a DQS butter
7
, a mask buffer/latch
8
, an input/output buffer/register
9
, serial-parallel converters
10
and
11
, and a parallel-serial converter
12
.
The clock buffer receives a clock signal CLK from the exterior and outputs the received signal to a predetermined circuit as an internal clock signal ICLK. The command decoder 5 receives a command signal CMD, analyzes the received command and outputs the resultant as an internal command signal ICMD. The address buffer
6
receives an address signal AD, and outputs the received signal as an internal address signal IAD. The SDRAM does not adapt an address multiplex type; therefore, the address signal A/D is supplied once in every read operation and in every write operation.
The DQS buffer
7
receives a data strobe signal DQS, and outputs the received signal as an internal data strobe signal IDQS. The mask buffer/latch
8
, when an enable signal ENA is activated, accepts a data mask signal DM in synchronization with the internal data strobe signal IDQS. The mask buffer/latch
8
then outputs the accepted signal to the serial-parallel converter
10
. The input/output buffer/register
9
receives an output data signal DOUT in a read operation. When the enable signal ENA is activated, the received signal is output as a data signal DQ in synchronization with the internal data strobe signal IDQS. Moreover, the input/output buffer/register
9
, when the enable signal ENA is activated in a write operation, accepts a data signal DQ in synchronization with the internal data strobe signal IDQS. The accepted data is output as an input data signal DIN.
The serial-parallel converter
10
converts mask signals sequentially supplied from the mask buffer/latch
8
into a parallel form and outputs the resultant as an internal mask signal IDM. The serial-parallel converter
11
sequentially receives input data signals DN of serial form supplied from the input/output buffer/register
9
. The serial-parallel converter
11
converts the received signals into a parallel form, and outputs the resultant as a write data signal WDB. The parallel-serial converter
12
converts a read data signal RDB of parallel form, supplied from a sense buffer
16
into serial forms. The parallel-serial converter
12
sequentially outputs the resultants as output data signals DOUT.
The chip control unit
2
comprises a command latch
13
, a control circuit
14
, a data masking circuit
15
, the sense buffer
16
, and a write amplifier
17
.
The command latch
13
receives the internal command signal ICMD, and outputs a read control signal RD, a write control signal WR, and the like, in accordance with the received signal. The control circuit
14
receives the read control signal RD and the write control signal WR, and outputs the enable signal ENA and a plurality of timing signals. The timing signals are supplied to the sense buffer
16
and the write amplifier
17
, along with row decoders
19
, sense amplifiers
20
, and column decoders
21
in the memory core units
3
.
The data masking circuit
15
masks a predetermined bit or bits of the write data signal WDB in accordance with the internal mask signal IDM. The masked signal is output as a write data signal WDBM.
The sense buffer
16
receives a data signal DB from the memory core units
3
, and outputs the received signal as the read data signal RDB in synchronization with the timing signal. The write amplifier
17
receives the write data signal WDBM, and outputs the received signal as a data signal DB in synchronization with the timing signal.
The memory core units
3
each comprise a memory cell unit
18
, the row decoder
19
, the sense amplifier
20
, and the column decoder
21
. The memory cell unit
18
includes a plurality of memory cells MC.
The row decoder
19
receives the timing signal and a predecoding signal generated from the internal address signal IAD and activates word lines WL connected with the memory cells MC. The column decoder
21
receives the timing signal and the predecoding signal generated from the internal address signal IAD and activates column switches (not shown) connected with bit lines BL. The sense amplifier
2
amplifies data transmitted from the memory cells MC through the bit lines BL in a read operation and amplifies the data signal DB supplied in a write operation.
FIG. 2
shows an example where the SDRAM described above executes a write operation between read operations. In this example, the read latency, which is a number of clocks from the reception of a read command to the output of read data, is “2”. The write latency, which is a number of clocks from the reception of a write command to the reception of write data, is “0”.
In the following descriptions, some abbreviations may be used such as “CLK signal” for the “clock signal CLK”.
For a start, read commands RD
0
and RD
1
are sequentially supplied in synchronization with the CLK signal to operate the memory core units
3
(FIG.
2
(
a
)). Read addresses not shown are supplied along with the read commands. The memory core units
3
output read data approximately one clock after the reception of the respective read commands. Subsequently, input/output circuit is operated (FIG.
2
(
b
)). Here, the input/output circuit corresponds to the sense buffer
16
, the parallel-serial converter
12
, and the input/output buffer/register
9
shown in FIG.
1
.
Then, read data Q
00
, Q
01
, Q
10
, and Q
11
are sequentially output as the data signals DQ, two clocks after the reception of the respective read commands RD
0
and RD
1
. The read data Q
00
and Q
01
, as well as Q
10
and Q
11
, are generated by the parallel-serial converter
12
converting the read data RDB of parallel form.
Subsequently is supplied a write command. Since the terminals to transmit those DQ signals are input/output terminals, write data DA
0
and DA
1
cannot be supplied until after the output of the read data Q
11
for the sake of avoiding a signal conflict. Besides, with the write latency at “0”, the write command WRA is supplied in synchronization with the same CLK signal as the write data DA
0
(FIG.
2
(
c
)). Though omitted of specific illustration, a write address is supplied along with the write data.
After the reception of the write command WRA, input/output circuit is operated to convert the write data DA
0
and DA
1
into a parallel form. The converted write data WDB are masked for a predetermined bit or bits by the
Arent Fox Kintner & Plotkin & Kahn, PLLC
Fears Terrell W.
Fujitsu Limited
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