Static information storage and retrieval – Read/write circuit – Bad bit
Reexamination Certificate
1997-12-31
2001-06-26
Zarabian, A. (Department: 2824)
Static information storage and retrieval
Read/write circuit
Bad bit
C365S225700, C365S230030, C365S230060
Reexamination Certificate
active
06252808
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor memory device, and more particularly, to a semiconductor memory device having a row redundancy scheme and a method for curing a defective cell.
2. Description of the Related Art
In a general semiconductor memory device with many memory cells, when a memory cell is defective either in manufacturing or later, the memory chip malfunctions and therefore cannot be used. Each memory device is therefore equipped with a curing mechanism which is based upon a redundancy scheme.
Also, as semiconductor memory device technology improves, a greater number of cells are being arranged on a single chip and large integrated circuits are being fabricated. Accordingly, the chance of a defective memory cell in a chip is increasing, and therefore the need for curing of a defective cell in a highly integrated memory is more important than ever for providing a higher yield of the chip.
To avoid defective memory cells from causing the memory chip to malfunction, in a conventional semiconductor memory device, the redundancy scheme includes providing redundancy memory cells as well as basic memory cells. In volatile memory, these redundancy cells are charged in an on-going basis in the same manner as the basic memory cells when and in the event that the redundancy memory cells are used to replace the defective normal memory cells so as to maintain normal operation of the memory device. A circuit called a fuse box is used to replace a defective memory cell with a redundancy memory cell. For greater redundancy, the number of redundancy memory cells and fuse boxes are increased, or several memory cell blocks share a predetermined number of redundancy memory cells and fuse boxes.
FIG. 1
is a block diagram of a memory device having a conventional row redundancy scheme. Here, several memory cell blocks share redundancy cells and fuse boxes. Referring to
FIG. 1
, the conventional memory device has a row redundancy scheme which includes a precharger
110
, a plurality of global memory cell array blocks
100
and a redundancy enabling portion
120
.
In particular, the conventional memory device includes a delay unit (which is part of block selector
160
) which operates to suspend normal decoder operations during a redundancy mode operation by redundancy enabling portion
120
. Below is a description of how the redundancy scheme operates in a convention memory device. As will be discussed below, a conventional redundancy scheme has the disadvantage that during the suspension of coding redundancy operations, the main memory is slowed down.
In the precharger
110
, when a “low” or “high” signal is input into a predetermined row address, a low precharge signal RPS is activated. The redundancy enable portion
120
is precharged by the RPS, and responds to a redundancy signal REDi (I=0, 1, . . . , n), which is an output signal of respective global memory cell array blocks
100
. Accordingly, when a row redundancy scheme of a global memory cell array block is selected and operated, a row redundancy enable signal RREB becomes activated.
The global memory cell array block
100
is includes a normal block
130
, a redundancy block
140
, a fuse box
100
a
, a redundancy driver
150
, a block selector
160
, a normal word line enabling portion
100
b
and a normal decoder
100
c
. The normal block
130
includes many memory cells arranged in rows and column. The redundancy block
140
also includes many memory cells arranged in rows and column, and is selected and operated if a cell in the normal block
130
is defective.
FIG. 2
shows the fuse box
100
a
in greater detail. The fuse box
100
a
responds to the RPS signal to be precharged and generates the redundancy signals REDi (I=0, 1, . . . , n) responding to all row address signals of RAi (I=0, 1, . . . , n−1). When the address of a memory cell which normally operates in the normal block is selected, a logic state of the redundancy signal REDi (I=0, 1, . . . , n) goes to “LOW”. However, when the address of a defective cell of the normal block is selected, a fuse of a corresponding address shorts. Accordingly, in the second case, a logic state of the redundancy signal REDi (I=0, 1, . . . , n−1) is kept “HIGH” and the redundancy scheme is used.
The normal word line enabling portion
100
b
is shown in FIG.
3
. Here, the normal operation mode, the redundancy signal REDi is “LOW” and a block select signal BLSi of the selected global memory cell array block is “HIGH”. Accordingly, a normal word line enable signal NWE output from the normal wordline enable portion
100
b
goes to “HIGH”, to enable the normal word line.
The normal decoder
100
c
is shown in FIG.
4
. During an initial operation, as shown in
FIG. 4
, the normal decoder
100
c
is precharged by the RPS. Also, when the NWE is “HIGH”, the normal decoder responds to the row address signal RAi (I=0, 1, . . . , n−1), to enable a word line WLij of a corresponding memory cell of the normal block
130
.
However, as discussed above, the block selector
160
for generating the block select signal BLSi includes a delay unit. Since operation of the normal coder during a redundancy would cause a malfunction the delay unit prevents such operation.
Accordingly, in the conventional memory device having a row redundancy scheme, the NWE operates the normal decoder, through a delay path of REDi-RREB-BLSi-NWE, and further a delay unit is included in the block selector
160
. As a result, the enabling of a word line is disadvantageously delayed even in a normal path. Also, since a defective cell is always replaced with a redundancy cell from the same global block, the efficiency is low.
SUMMARY OF THE INVENTION
Objects of this invention include providing a semiconductor memory device having a redundancy scheme in which the time to enable a word line in a normal path is less than that of a conventional device, enhancing the operation speed of a memory chip, and maximizing the number of common redundancies to enhance the redundancy capability. (Common redundancies refer to the fact that a redundancy block can replace normal columns in multiple memory blocks, and thus is common to those memory blocks.)
It is another object of the present invention to provide a method for curing a defective cell.
To accomplish the above objects of the present invention, this invention provides a semiconductor memory device which allows both to a redundancy block substantially without interruption of normal cell block operations.
More particularly, this invention includes a plurality of global blocks, each of which including a plurality of unit matrixes having of a normal block formed by array of normal cells and a redundancy block formed by array of redundancy cells. The global block includes a normal division word line driver for driving the word line of the normal cells. The global block also includes a redundancy division word line driver for driving the word line of the redundancy cells. The global block further includes a main decoder for supplying an output signal to the normal division word line driver. In particular, the global block of this invention includes an auxiliary decoder for supplying an output signal to both the normal division word line driver and the redundancy division word line driver.
In the main decoder, an output signal is selectively activated according to a row address signal regardless of using the redundancy cell. Also, in the auxiliary decoder, when a corresponding global block is selected according to the row address signal for selecting a global block in a normal operation mode or a redundancy scheme of the corresponding block is used in the redundancy operation mode, an output signal is selectively activated according to the row address signal.
To further accomplish objects of the present invention, there is provided a method for curing a defective cell of a semiconductor memory device using a plurality of global blocks each comprising two or more un
Marger & Johnson & McCollom, P.C.
Samsung Electronics Co,. Ltd.
Zarabian A.
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