Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-07-22
2001-04-10
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S700000, C438S588000, C438S589000
Reexamination Certificate
active
06214669
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention generally relates to a single-chip contact-less read-only memory (ROM) device and a method for fabricating the device, and more particularly to a single-chip contact-less ROM device having a structure such as a flash memory, and the method for fabricating the device.
Description of the Related Art
A single-chip semiconductor memory device, regardless of the type of memory (e.g., a random access memory (RAM), a read only memory (ROM), etc.), normally includes a plurality of memory cell arrays, peripheral circuits for operating the memory cell arrays, and connecting portions for electrically connecting the memory cell arrays, and connecting between one of the memory cell arrays and one of the peripheral circuits.
However, every memory cell of a ROM does not need contact holes for connecting a corresponding memory cell and a bit line (e.g., metal wiring), although every memory cell of a RAM must have the contact holes. Therefore, “a contact-less memory device” has been developed mainly as a ROM.
As the contact-less memory device, Japanese Patent Application Laid-Open No. Hei 6-283721 discloses a memory cell array having a plurality of electrically erasable and programmable ROM (EEPROM) cells, and having a construction as “a flash memory”. The memory device having such a flash memory construction is also disclosed in U.S. Pat. No. 5,595,924.
However, gates of the EEPROM cells have a larger thickness than gates of metal oxide-semiconductor (MOS) transistors which are used for the peripheral circuit or for the connecting portion. Therefore, a surface of an insulating film formed on a semiconductor substrate becomes irregular (e.g., not flat, uneven rough furface), because the EEPROM cells for the memory cell array and MOS transistors for the connecting portion or for the peripheral portion are formed on the same level of the semiconductor substrate in the conventional devices.
When such an irregularity occurs, it is difficult to form wirings (e.g., bit lines) on the insulating film by photo-lithography.
In contrast to the above-mentioned memory cell array, Japanese Patent Application Laid-Open No. Hei 4-164368 discloses a memory cell array having a plurality of “stacked capacitors”. The memory cell arrays are formed on a first level which is lower than the level of the original surface of the semiconductor substrate. Therefore, an irregularity of an insulating film formed on a substrate including the stacked capacitors becomes small.
However, the depths are different between a contact hole connecting a peripheral circuit and a bit contact hole, because the contact hole is formed on the original surface and the bit contact hole is formed on the first level. Therefore, an aspect ratio of the bit contact hole must be different from an aspect ratio of the contact hole connecting a peripheral circuit. This is a problem.
SUMMARY OF THE INVENTION
In view of the foregoing and other problems of the conventional structure, it is therefore an object of the present invention to provide an improved single-chip memory device.
It is another object of the present invention to provide an improved single-chip contact-less flash memory device.
It is yet another object of the present invention to provide an improved method for fabricating a single-chip contact-less memory device.
In a first aspect, a single-chip memory device, according to the present invention, includes a semiconductor chip having a first surface and a second surface located at a lower level than that of the first surface, a memory cell array formed on the second surface, a peripheral circuit, for operating the memory cell array, formed on the first surface, and a connecting portion, for electrically connecting the memory cell array to the peripheral circuit, formed on the first surface.
With the unique and unobvious structure of the present invention, the memory cell array is formed on the second surface, and the peripheral circuit and the connecting portion are formed on the first surface. Therefore, the surface of device can be made flat (e.g., regular). As a result, a small memory device can be obtained.
REFERENCES:
patent: 4642880 (1987-02-01), Mizutani et al.
patent: 4882289 (1989-11-01), Moriuchi et al.
patent: 5496758 (1996-03-01), Ema
patent: 5780310 (1998-07-01), Koyama
patent: 5780340 (1998-07-01), Gardner et al.
patent: 5828120 (1998-10-01), Ishikawa
patent: 5886376 (1999-03-01), Acovic et al.
patent: 4-164372 (1992-06-01), None
patent: 4-164368 (1992-06-01), None
patent: 6-283721 (1994-10-01), None
Elms Richard
McGinn & Gibb PLLC
NEC Corporation
Pyonin Adam
LandOfFree
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