Semiconductor memory device having a single transistor two...

Details Semiconductor memory device having a single transistor two... Semiconductor memory device having a single transistor two...

1999-07-13

2001-01-09

Elms, Richard (Department: 2824)

Static information storage and retrieval

Read/write circuit

Precharge

C365S230030, C365S185230

Reexamination Certificate

active

06172922

ABSTRACT:

BACKGROUND OF THE INVENTION
This invention relates to a semiconductor memory device and, in particular, to selection of a memory cell and a bus precharge method in a semiconductor memory device using flat memory cells.
FIG. 1
is a circuit diagram of a memory cell array and a peripheral circuit thereof in a semiconductor memory device using flat memory cells. As shown in the figure, the illustrated circuit comprises a memory cell array
108
, a sense amplifier
111
(the block will later be illustrated), a Y selector circuit
110
, a GND selector circuit
107
, precharge circuits
105
and
112
(the blocks will later be illustrated), and precharge selector circuits
106
and
109
.
Next, a traditional operation upon selection of a memory cell will briefly be described. At first, a word line and a bank select line are selected. The Y selector circuit
110
selects a digit line DG
0
while the GND selector circuit
107
selects a GND line VG
0
. An electric current from the sense amplifier
111
to the GND line GND in the above-mentioned state is represented by a current path IL
1
. At this time instant, a selected memory cell C
0
is determined. If the selected memory cell C
0
is an OFF bit (memory cell through which no electric current flows), an electric current does not flow from the sense amplifier
111
towards the GND line GND. However, if memory cells C
1
, C
2
, C
3
, . . . , Cn successively adjacent to the memory cell C
0
are ON bits (memory cells through which an electric current flows), the electric current flows towards a current path IL
2
as illustrated in the figure to inhibit the operation of the sense amplifier
111
.
In order to suppress the above-mentioned phenomenon, the precharge circuit
105
is used. The precharge selector circuit
106
precharges a GND line VG
1
adjacent to a selected data bus line to a level equal to that of the selected digit line DG
0
. Thus, a current flow towards the current path IL
2
is interrupted. In order to detect a small current by the sense amplifier
111
, it is necessary to minimize the amount of the electric current flowing through the current path IL
2
illustrated in FIG.
1
. For this purpose, a digit line DG
1
may be precharged by the precharge circuit
112
and the precharge selector circuit
109
, in addition to the GND line VG
1
.
PROBLEM TO BE SOLVED BY THE INVENTION
In the above-mentioned conventional semiconductor memory device using flat memory cells, the precharge circuit
105
is essential. In addition to the Y selector circuit
110
and the GND selector circuit
107
, the precharge selector circuit
106
is required. Furthermore, in addition to the precharge circuit
105
and the precharge selector circuit
106
for precharging the GND line GND, the precharge circuit
112
and the precharge selector circuit
109
for selective precharge of a digit line are required.
It is an object of this invention to implement by a single transistor two functions as a Y selector of a Y selector circuit and a precharge selector of a precharge selector circuit for selective precharge of a digit line and to implement with a single transistor a GND selector of a GND selector circuit and a precharge selector of a precharge selector circuit for precharging a GND line, so that only one selector transistor is required to be connected to each of a single digit line and a single GND line, thereby reducing the number of transistors used in a memory and suppressing an increase in layout area.
MEANS TO SOLVE THE PROBLEM
According to this invention, there is provided a semiconductor memory device comprising a memory cell array using flat memory cells, a sense amplifier connected to the memory cell array, a GND selector circuit arranged in the vicinity of the memory cell array and connected to the memory cell array, a precharge circuit, and a precharge selector circuit connected to the GND selector circuit and the precharge circuit, wherein the memory cell array and the GND selector circuit are connected via a metal wiring, the GND selector circuit having selectors each of which is a single transistor connected to one metal line of the metal wiring, the GND selecting transistor of the GND selector circuit being commonly used as a precharge selecting transistor of the precharge selector circuit.
According to this invention, there is also provided a semiconductor memory device comprising a memory cell array using flat memory cells, a sense amplifier, a Y selector circuit connected to the sense amplifier, a precharge circuit, and a precharge selector circuit, wherein the memory cell array and the Y selector circuit are connected to digit lines, the Y selector circuit having selectors each of which is a single transistor connected to each single digit line among the digit lines, the digit line selecting transistor of the Y selector circuit being commonly used as a precharge line selecting transistor of the precharge selector circuit.
According to this invention, there is also provided a semiconductor memory device comprising a memory cell array using flat memory cells, a sense amplifier connected to the memory cell array, a GND selector circuit arranged in the vicinity of the memory cell array and connected to the memory cell array, a first precharge circuit, a first precharge selector circuit connected to the GND selector circuit and the first precharge circuit, a Y selector circuit connected to the sense amplifier, a second precharge circuit, and a second precharge selector circuit, wherein the memory cell array and the GND selector circuit are connected via a metal wiring, the GND selector circuit having selectors each of which is a single transistor connected to one metal line of the metal wiring, the GND selecting transistor of the GND selector circuit being commonly used as a precharge selecting transistor of the precharge selector circuit, the memory cell array and the Y selector circuit being connected to digit lines, the Y selector circuit having selectors each of which is a single transistor connected to one digit line among the digit lines, the digit line selecting transistor of the Y selector circuit being commonly used as the precharge line selecting transistor of the precharge selector circuit.


REFERENCES:
patent: 4811301 (1989-03-01), Houston
patent: 5369620 (1994-11-01), Sugibayashi
patent: 5621697 (1997-04-01), Weng et al.
patent: 5703820 (1997-12-01), Kohno
patent: 5768199 (1998-06-01), Inoue
patent: 5771190 (1998-06-01), Okamura

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