Method for manufacturing bit line and bit line contact

Details Method for manufacturing bit line and bit line contact Method for manufacturing bit line and bit line contact

1999-09-13

2001-07-03

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S617000, C438S618000

Reexamination Certificate

active

06255168

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method for manufacturing a bit line. More particularly, the present invention relates to a method for manufacturing a bit line and a bit line contact.
2. Description of the Related Art
To isolate a bit line contact inside an alignment window from a word line, a silicon nitride spacer is usually formed on the sidewall of the word line. The spacer is in contact with the sidewall of the word line as well as the silicon substrate. Due a difference in lattice constant between silicon nitride and polysilicon, considerable internal stress is created along the boundary between the silicon nitride spacer and the word line as well as between the silicon nitride spacer and the silicon substrate. Therefore, a large number of lattice defects are produced along their boundary regions.
FIGS. 1A and 1B
are schematic cross-sectional views showing the steps for producing a conventional bit line and bit line contact above a substrate.
As shown in
FIG. 1A
, a word line
102
is formed above a substrate
100
. The word lines
102
are formed by depositing a polysilicon layer
104
and a metal silicide layer
106
in sequence. In general, a silicon nitride layer
108
is also formed on the top surface of the word lines
102
serving as an additional protective layer. Silicon nitride spacers
110
are formed on the sidewalls of the word lines
102
. The entire substrate
100
and the word lines
102
are covered by a dielectric layer
112
. Utilizing the sidewall spacers
110
, a self-aligned contact window
114
that exposes a portion of the substrate
100
is formed in the dielectric layer
112
.
As shown in
FIG. 1B
, a polysilicon layer
116
that also fills the contact window
114
is formed over the dielectric layer
112
. A metal silicide layer
118
(for example, a tungsten silicide layer) is formed over the polysilicon layer
116
. Finally, polysilicon layer
116
and the metal silicide layer
118
are patterned to form a bit line.
In the aforementioned method of forming a bit line and a bit line contact, silicon nitride spacers are formed on the sidewalls of the word line. Due to stresses at the contact region between polysilicon and silicon nitride, many dislocations are formed, often resulting in the production of a large leakage current. In addition, the polysilicon layer
116
and the metal silicide layer
118
of the bit line are formed above the dielectric layer
112
. Moreover, the silicon nitride layer
108
over the word line
102
also adds a little more thickness to the overall height of a memory cell unit. The resulting processing window of the method is therefore severely limited.
SUMMARY OF THE INVENTION
The invention provides a method for manufacturing a bit line and a bit line contact. A semiconductor substrate having a word line thereon is provided. Oxide spacers are formed on the sidewalls of the word line. A dielectric layer that covers the word line is formed over the entire substrate. A cap layer is next formed over the dielectric layer. The cap layer and the dielectric layer are patterned to form a trench in the dielectric layer. Silicon nitride spacers are formed on the sidewalls of the trench. In the subsequent step, the dielectric layer is etched via the trench to form a contact window that exposes a portion of the substrate. Polysilicon material is deposited into contact window to form a polysilicon plug, and then metal silicide material is deposited into the trench above the plug to form a metal silicide layer.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 5741722 (1998-04-01), Lee
patent: 6071804 (2000-06-01), Gau
patent: 6096594 (2000-08-01), Lin et al.

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