Active solid-state devices (e.g. – transistors – solid-state diode – Lead frame – With stress relief
Reexamination Certificate
1997-12-05
2001-03-13
Chaudhuri, Olik (Department: 2814)
Active solid-state devices (e.g., transistors, solid-state diode
Lead frame
With stress relief
C257S676000, C257S738000, C257S778000
Reexamination Certificate
active
06201294
ABSTRACT:
This application claims the benefit of Korean Application Number 75051/1996 filed on Dec. 28, 1996, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor package, and more particularly, to a ball grid array (hereinafter, “BGA”) semiconductor package and method of fabricating the same.
2. Description of the Related Art
A quad flat package (hereinafter, “QFP”) has received great attention as part of a multipin trend in the semiconductor packaging technology. The width of outer leads becomes narrower and the pitch between the leads become minute in the QFP. The leads are, however, easily bent and the package is hard to align on a printed circuit board (PCB) when the leads are surface-mounted on the PCB. Moreover, it is difficult to control the amount of solder in the manufacturing process.
Accordingly, a BGA semiconductor package has been developed to solve the problems of the QFP. The BGA semiconductor package has solder balls instead of the outer leads, so that the disadvantages of the QFP can be overcome.
FIG. 1
is a longitudinal cross-sectional view showing a conventional BGA semiconductor package. The conventional BGA semiconductor package includes a substrate
1
having a plurality of inner leads (not illustrated) in a form of miniature wirings, a semiconductor chip
2
attached on the upper surface of the substrate
1
using an adhesive
3
, a plurality of conductive wires
4
electrically connecting the semiconductor chip
2
and each one end of the inner leads disposed in the substrate, a molding unit
5
sealing a predetermined region of the upper surface of the substrate
1
with an epoxy molding compound to encapsulate the semiconductor chip
2
and the wires
4
, and a plurality of solder balls
6
formed on the lower surface of the substrate
1
and connected with the other end of each inner lead in the substrate
1
.
However, the conventional BGA semiconductor package employs the substrate
1
having the inner leads disposed therein, and the substrate
1
will already have absorbed moisture during the fabricating process of conductive layers and an insulating layers through an etching process. Accordingly, delamination and cracking caused by vapor pressure inside the substrate reduce the reliability of the semiconductor package. Further, since the epoxy molding unit
5
is formed only on the upper surface of the substrate
1
, delamination occurs easily at the boundary surface of the substrate
1
and the molding unit
5
.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a ball grid array (BGA) semiconductor package that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention to provide an improved BGA semiconductor package and method of fabricating the same by using a lead frame instead of a substrate to avoid delamination and exfoliation of the package caused by the substrate.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularly pointed out in the written description and claims hereof as well as the appended drawings.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, the BGA semiconductor package includes a paddle, a semiconductor chip attached on the upper surface of the paddle using an insulating adhesive, a plurality of first leads arranged to have a constant interval therebetween around the peripheral portion of the paddle and one end of each of which is bent downward, a plurality of second leads attached on the lower surfaces of the first leads, a plurality of conductive wires electrically connecting the semiconductor chip and the first leads, a molding unit sealing the entire structure in such a manner that a portion of the lower surface of each of the second leads is externally exposed, and a plurality of solder balls respectively attached on the exposed lower surfaces of the second leads.
In another aspect, the ball grid array semiconductor package includes a paddle, a semiconductor chip on the paddle, a plurality of first leads around a periphery of the paddle, a plurality of second leads attached to a lower surface of each of the first leads, a plurality of conductive wires electrically connecting the semiconductor chip and the first leads, a molding unit sealing the paddle, the semiconductor chip, the first leads, the second leads, and the conductive wires, except for a lower portion of the second leads, and a plurality of solder balls attached to the lower portion of the second leads.
In another aspect, the ball grid array semiconductor package includes a semiconductor chip, a paddle on the semiconductor chip, a plurality of first leads around a periphery of the paddle, a plurality of second leads attached to a lower surface of each of the first leads, a plurality of conductive wires electrically connecting the semiconductor chip and the first leads, a molding unit sealing the paddle, the semiconductor chip, the first leads, the second leads, and the conductive wires, except for a lower portion of the second leads, and a plurality of solder balls attached to a lower portion of the second leads.
In a further aspect, the method of fabricating a ball grid array (BGA) semiconductor package having first and second frames, includes the steps of attaching a semiconductor chip to a paddle located on the first frame, electrically connecting a plurality of first leads to the semiconductor chip, electrically connecting a plurality of second leads to the plurality of first leads, aligning a first junction unit of the first frame with a second junction unit of the second frame, attaching the first frame to the second frame, molding the first and second frames, and attaching a plurality of solder balls to each of a plurality of second leads.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.
REFERENCES:
patent: 5157480 (1992-10-01), McShane
patent: 5541450 (1996-07-01), Jones et al.
patent: 5578871 (1996-11-01), Fierkens
patent: 5594234 (1997-01-01), Carter, Jr. et al.
patent: 5619065 (1997-04-01), Kim
patent: 5736780 (1998-04-01), Murayama
patent: 5770888 (1998-06-01), Song et al.
patent: 5825628 (1998-10-01), Garbelli et al.
patent: 5894107 (1999-04-01), Lee et al.
patent: 5898212 (1999-04-01), Kim
patent: 5926696 (1999-07-01), Baxter et al.
patent: 40 6013485 (1994-01-01), None
patent: 40 6163607 (1994-06-01), None
Chambliss Alonzo
Chaudhuri Olik
Hyundai Electronics Industries Co,. Ltd.
Morgan & Lewis & Bockius, LLP
LandOfFree
Ball grid array semiconductor package comprised of two lead... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Ball grid array semiconductor package comprised of two lead..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Ball grid array semiconductor package comprised of two lead... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-2441950