Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-03-13
2001-05-01
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S769000, C438S776000, C438S775000, C438S911000
Reexamination Certificate
active
06225167
ABSTRACT:
BACKGROUND OF THE INVENTION
(1) Field of the Invention
The present invention relates to the manufacture of semiconductor devices in general, and in particular, to a method of using NH
3
nitridation followed by re-oxidation to generate different oxide thicknesses in a semiconductor device by one oxidation step.
(2) Description of the Related Art
Oxides in semiconductor devices play an extremely important role both in terms of providing a passive insulative barrier among various parts in the devices as well as performing an active function for the parts. Thus, simply separating different layers of metal from one another is an example of the former, while providing a particular capacitance value to a device is an example of the latter. Generally, a much greater portion of a semiconductor substrate comprises oxides, and therefore contributes to its size proportionately. Accordingly, forming oxides, with particular attention given to their dimensions,is important, especially in the field of ultra large scale integrated (ULSI) circuits, and semiconductor chips, as is well known. It is disclosed in the present invention a method of forming oxides of multiple thicknesses in one step.
More specifically, as semiconductor processing technologies advance, device geometries of integrated circuits are continually made smaller so that the device density of the entire system can be maximized. This results in, for example, transistors within integrated devices such as MOSFETS having shorter and shorter gate lengths. This in turn necessitates a reduction in gate oxide thickness and operating supply voltage in order to support the minimum gate length without excessively high threshold voltages. The minimum allowable gate oxide thickness for a given device is limited by the time dependent dielectric breakdown of the thin oxide at the desired operating voltage. As a result, the operating voltages applied to the gates of transistors within a particular device must be reduced as the gate oxides within these devices are reduced in thickness, as is known in the art.
Furthermore, it has become necessary to integrate different gate oxide thicknesses onto a single integrated circuit device. This is because, high performance transistors require thinner gate dielectric regions and operate at lower voltages (e.g. 1.8 volts to 2.5 volts), whereas most conventional external peripherals typically require higher operating voltages such as 3.3 volts to 5.0 volts. When interfacing lower voltage high performance MOS transistors to higher voltage devices, input and output (I/O) buffers of the integrated circuit (IC) are typically designed to contain thicker gate dielectric regions that are compatible with the higher external peripheral device voltages. In addition, current micro-controller units (MCUs) and digital signal processors (DSPs) are integrating several different types of technology onto a single integrated circuit. For example, high speed logic, power logic, static random access memory (SRAM), nonvolatile memory (NVM), embedded dynamic random access memory (DRAM), analog circuitry, and other devices and technologies are now being considered for integration onto the same integrated circuit die. Many of these devices require different gate dielectric processing and different gate dielectric thicknesses.
Forming of gate oxide layers having two different thicknesses on the same substrate can be difficult. Conventionally, photolithographic techniques are employed to pattern separately the oxides that are to have different thicknesses. It is often the case, however, that with the required two different oxide thicknesses, there are times when a photoresist mask is placed in proximity to the bare semiconductor substrate. The photoresist is known to cause degradation of the surface of the substrate, which is not desirable especially in the area intended to be used for high performance transistors. In its place, Holloway, et al., in U.S. Pat. No. 5,989,962 disclose a method of using nitride as a mask. Specifically, a gate insulator (oxide) is formed. The outer surface of the gate insulator is then masked such that only the portions of the gate insulator layer to be used for low voltage devices are exposed. The exposed portion of the gate insulator layer is then processed to create a nitride layer. The masking material is then removed. An additional gate insulator layer is then grown to increase the thickness of the dielectric of the portion of the insulator layer associated with high voltage devices. The nitride layer is used to advantage because of its characteristics to inhibit the growth of the underlying oxide in the area of the insulator layer to be used for low voltage devices.
The advantages of using a nitride or an oxynitride layer to self-limit the growth of the proximate oxide layer is known in the art, and it has been used for enhancing the physical and electrical properties of tunnel oxides. As is known, tunnel dielectric layer is used to separate the floating gate of a memory cell from the channel in the substrate and hold the charge transferred into the floating gate. Reducing the thickness of the tunnel dielectric is of primary importance to the development of high density nonvolatile memory devices. With all methods for transferring a charge to a floating gate depends upon the capacitance between the floating gate and the control gate which, in turn, depends upon the thickness of the tunnel dielectric layer. In order to minimize the amount of energy needed to transfer a charge into and out of the floating gate, as well as to minimize the amount of heat generated by the device during programming, it is desirable to minimize the thickness of the tunnel dielectric layer. One common approach is to form an oxynitride layer at the silicon-oxide interface during fabrication of the memory cells. The presence of the oxynitride layer limits the oxidation of silicon and thus enables a silicon dioxide layer of a limited thickness to be grown. This results in a thinner tunnel oxide, including improved physical properties.
Chang, et al., of U.S. Pat. No. 5,834,351 point out, however, that formation of oxynitride layer during fabrication of the memory cells has the disadvantage of introducing nitrogen particles embedded in oxides, such as in field oxides separating individual transistors from each other in a substrate, and in areas peripheral to the regions of the device where memory cells are being formed. In these peripheral regions, the residual nitrogen limits the growth of silicon dioxide in subsequent oxide growth processes. For example, the presence of residual nitrogen can cause thinning of peripheral gate oxide formation adjacent field oxides. Thinning of peripheral gate oxides can cause earlier breakdown in the peripheral circuits which is not desirable. Thus, in order to prevent the neighboring regions from this “nitrogen contamination”, Chang, et al., disclose a process where they confine the oxynitride layer to the desired regions of the integrated circuit only. For this purpose, an oxynitride layer is selectively formed in a memory array region without leaving residual oxynitride layers in regions peripheral to the memory array region. In one approach to the process, an oxynitride is selectively formed in a memory array region such that little or no oxynitride is formed in peripheral regions. In an alternate approach, any oxynitride layers formed in peripheral regions are selectively removed.
A conventional method of forming two different gate oxide thicknesses in two different active areas is illustrated in
FIGS. 1
a
-
1
d
.
FIG. 1
a
shows a partial cross-section of a semiconductor substrate, (
10
). Trench isolation regions (
15
) are formed within select portions of the substrate (
10
). The trench isolation regions (
15
) separate many active areas of the substrate (
10
), two of which are illustrated in FIG.
1
a. Specifically,
FIG. 1a
illustrates a first active area (
50
) that is separated from a second active area (
40
) by one or more trench isolation regions (
15
), as delineated by
Chen Wei-Ming
Yu Mo-Chiun
Ackerman Stephen B.
Elms Richard
Oktay Sevgin
Pyonin Adam
Saile George O.
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