Methods of operating ferroelectric memory devices having...

Details Methods of operating ferroelectric memory devices having... Methods of operating ferroelectric memory devices having...

2000-05-08

2001-04-10

Tran, Andrew (Department: 2824)

Static information storage and retrieval

Systems using particular element

Ferroelectric

C365S149000, C365S202000, C365S210130

Reexamination Certificate

active

06215693

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to integrated circuits and more particularly to integrated circuit memory devices and methods of operating integrated circuit memory devices.
BACKGROUND OF THE INVENTION
Ferroelectric random access memory (FRAM) devices are “nonvolatile” memory devices because they preserve data stored therein, even in the absence of a power supply signal. Each memory cell includes a capacitor composed of a ferroelectric material. The ferroelectric capacitor is composed of two conductive layers and a ferroelectric material layer formed therebetween. The ferroelectric materials used for the ferroelectric capacitor are typically Phase III potassium nitrate, bismuth titanate and lead zirconate titanate Pb(Zr, Ti)O
3
(PZT). Ferroelectric materials have hysteresis characteristics. Thus, the polarity of the ferroelectric material can be maintained even after interruption of the power supply. Data (e.g., logic 0,1) is stored in the FRAM as the polarity state of the ferroelectric material in each capacitor.
The typical hysteresis characteristics of the ferroelectric material will be described in detail with reference to FIG.
1
. In
FIG. 1
, the abscissa represents a voltage V applied across the electrodes of the ferroelectric capacitor, and the ordinate represents an amount of electric charge Q stored in the ferroelectric capacitor. The polarity-electric field (P-E) characteristics of the ferroelectric material is also similar to that of the Q-V characteristics shown in FIG.
1
.
Due to the hysteresis characteristic of the ferroelectric capacitor, current passing through a capacitor is changed by the history of the voltage applied thereto. For example, assuming that the S
4
state corresponds to data “1”, the S
1
state corresponds to data “0”, the state of the ferroelectric capacitor is transferred from state S
4
to state S
5
and then to state S
6
by application of a negative voltage. During this transfer, the electric charge amount Q
R
accumulated in the ferroelectric capacitor is changed to −Q
R
. At this time, a change of the accumulated charge becomes −2Q
R
, and accordingly a voltage of a bit line is changed as shown in formula (1):
Δ
⁢
 
⁢
V
(
1
)
=
2
⁢
Q
R
C
BL
Here, C
BL
represents an equivalent capacitance of a bit line coupled to the ferroelectric capacitor.
However, in the event the ferroelectric capacitor is in the S
1
state corresponding to data “zero”, and then a negative voltage is applied, the S
1
state is changed to the S
6
state and the change in accumulated electric charge is slight. Thus, the change in potential of the bit line is negligible.
The hysteresis characteristic of the ferroelectric capacitor will now be described in more detail as follows. Assuming that an initial state of the ferroelectric capacitor is S
1
in
FIG. 1
, if the voltage applied to the ferroelectric capacitor is increased, the state of the ferroelectric capacitor will transition from state S
1
to state S
2
. The voltage applied to the ferroelectric capacitor in state S
2
is typically referred to as the coercive voltage. If the intensity of the voltage applied to the ferroelectric capacitor is increased beyond the coercive voltage, the state of the ferroelectric capacitor will change from state S
2
to state S
3
. In state S
3
, the ferroelectric capacitor has a first polarization which Is typically referred to as a positive polarization. As illustrated by
FIG. 1
, the removal of the positive voltage from a ferroelectric capacitor in state S
3
will cause the capacitor to transition from state S
3
to state S
4
, however, the first polarization state will be maintained. Finally, if the voltage applied to a ferroelectric capacitor in state S
4
is made sufficiently negative, the state of the ferroelectric capacitor will transition to state S
5
and then to state S
6
. In state S
6
, the ferroelectric capacitor has a second polarization which is typically referred to as a negative polarization. As illustrated by
FIG. 1
, the removal of the negative voltage from a ferroelectric capacitor In state S
6
will cause the capacitor to transition from state S
6
to state S
1
, however, the second polarization state will be maintained. As will be understood by those skilled in the art, a ferroelectric capacitor in the first and second polarization states is typically referred to as storing data “1” and data “0”, respectively.
The polarization switching speed of a ferroelectric capacitor is approximately 10
−9
sec, and the necessary program time of the ferroelectric capacitor is typically shorter than that of other nonvolatile memory devices such as electrically programmable read only memory (EPROM) devices, electrically erasable and programmable read only memory (EEPROM) devices and flash memory devices. As will be understood by those skilled in the art, the read/write cycle endurance of a ferroelectric capacitor is typically on the order of 10
9
to 10
12
.
Conventional nonvolatile ferroelectric memory devices having ferroelectric capacitors will now be described with reference to
FIGS. 2-4
. In
FIG. 2
, a nonvolatile ferroelectric memory device includes nine memory cells. Each memory cell comprises one ferroelectric capacitor. The ferroelectric capacitor is connected between one of row lines R
0
, R
1
and R
2
and one of column lines C
0
, C
1
and C
2
. A memory cell having the ferroelectric capacitor
101
is selected by applying a positive voltage, for example, 5 Volts, to the row line R
0
and 0 Volts to the other row lines R
1
and R
2
. At this time, the positive voltage is applied to upper conductive layers of the ferroelectric capacitors
102
and
103
as well as that of the ferroelectric capacitor
101
. 0 Volts is applied to the column line C
0
. Accordingly, 5 Volts is applied across the ends of the selected ferroelectric capacitor
101
, which causes the ferroelectric capacitor
101
to be in a first polarization state. At this time, 0 Volts is applied across the ferroelectric capacitor
104
so that the polarization state is not changed. However, a voltage of approximately 2.5 Volts is applied to the respective column lines C
1
and C
2
so that the voltages applied across the ferroelectric capacitors
102
and
103
should not change polarization states. After completion of a reading operation of the memory cell formed of the ferroelectric capacitor
101
, an operation for restoring a state of initial polarization should be performed. Accordingly, 5 Volts is applied to the column line C
0
and 0 Volts is applied to the row line R
0
. Also, 2.5 Volts is applied to the row lines R
1
and R
2
and 0 Volts is applied to the column lines C
1
and C
2
. Accordingly, the nonvolatile ferroelectric memory device shown in
FIG. 2
requires a driving circuit for generating a sequence of various combinational voltages. The driving circuit is complicated and may impede the high speed operation of the memory device. The driving circuit may also require a wide layout area.
FIG. 3
shows another conventional nonvolatile ferroelectric memory device, where a memory cell includes one access transistor and one ferroelectric capacitor. One memory cell is formed in correspondence to an intersection of each of the bit lines BL
0
, BL
1
, BL
2
, . . . , BLn with each of the word lines WL
0
, WL
1
, . . . , WLn. In a memory cell
110
, a gate of an access transistor
111
is connected to the word line WL
0
, and a drain is connected to the bit line BL
0
. A ferroelectric capacitor
112
is connected between a source of the access transistor
111
and a plate line PL
0
. Plate lines PL
0
, PL
1
, . . . , PLn are alternately formed in parallel with the word lines WL
0
, WL
1
, . . . , WLn. A method for driving the nonvolatile ferroelectric memory device shown in
FIG. 3
is disclosed in an article by T. Sumi, et al. entitled A 256 kb Nonvolatile Ferroelectric Memory at 3 V and 100 ns, ISSCC Digest of Technical Papers, pp. 268-269, February (1994). In the nonvolatile ferroelectric memory device shown in
FIG. 3
, ferr

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