Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-06-30
2001-07-17
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06261901
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention relates to semiconductor technology, and more particularly, to cell capacitors for use in dynamic random access memories (DRAMs).
2. Description of the Related Arts
The circuit density on integrated circuits has continually increased over the years due to innovations in process technologies. One particular device with increased density is the dynamic random access memory (DRAM), which is expected to have more than a billion memory cells (gigabits) by the year 2000. This higher density of memory cells is a result of improved high resolution photolithography and patterning by directional (anisotropic) plasma etching, which result in reduced device sizes. However, this reduction in device size is putting additional demand on the semiconductor processing technologies, and also on maintaining the electrical requirements, such as maintaining or increasing the capacitance of capacitors on DRAM devices.
These DRAM devices consist in part of an array of individual DRAM storage cells that store binary data (bits) as electrical charge on a storage capacitor. Further, the information is stored and retrieved from the storage capacitor by means of a single pass transistor in each memory cell, and by address and read/write circuits on the periphery of the DRAM chip. The pass transistor is usually a field effect transistor (FET), and the single capacitor in each cell is either formed in the semiconductor substrate as a trench capacitor, or built over the FET in the cell area as a stacked capacitor. To maintain a reasonable DRAM chip size and improved circuit performance, it is necessary to further reduce the area occupied by the individual cells on the DRAM chip. Unfortunately, as the cell size decreases, it becomes increasing more difficult to fabricate stacked or trench storage capacitors with sufficient capacitance to store the necessary charge to provide an acceptable signal-to-noise level for the read circuits (sense amplifiers) to detect. Accordingly, this is a continuing challenge to maintain sufficiently high storage capacitance despite decreasing cell area.
The principle way of increasing cell capacitance is through cell structure techniques. Such techniques include three-dimensional cell capacitors, such as trenched or stacked capacitors. This invention concerns methods of forming three-dimensional cell capacitors.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method of forming a three-dimensional cell capacitor having greater capacitance per unit area.
Another object of the invention is to provide a method of forming a capacitor integrated with self-aligned contact having increased electrode surface area.
According to one embodiment, a capacitor opening is formed through a dielectric isolation interlayer to expose a buried contact area. A plug of conductive material is subsequently formed in a bottom portion of the capacitor opening and makes an electrical connection with the contact area. A conductive spacer is formed on the sidewall of the opening by depositing a conformal layer and anisotropically etching back, and such leaves a channel within the opening. A dielectric column is formed by filling the channel with dielectric material. The lateral surface of the dielectric column is then exposed by removing the laterally adjacent conductive spacer. Finally, first and second capacitor plates and a dielectric layer therebetween are formed within the capacitor opening and supported by the dielectric column, thereby completing the DRAM cell capacitor.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description which makes reference to the accompanying drawings.
REFERENCES:
patent: 5278091 (1994-01-01), Fazan et al.
Bowers Charles
Darby & Darby
Thompson Craig
Vabguard International Semiconductor Corporation
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