Self-aligned metal caps for interlevel metal connections

Details Self-aligned metal caps for interlevel metal connections Self-aligned metal caps for interlevel metal connections

1999-10-18

2001-07-17

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S626000, C438S633000, C438S660000, C438S661000, C438S674000, C438S685000, C438S681000, C438S688000

Reexamination Certificate

active

06261950

ABSTRACT:

BACKGROUND
1. Technical Field
This disclosure relates to semiconductor fabrication and more particularly, to a method and apparatus for an improved interface between metal lines by providing a metal cap.
2. Description of the Related Art
Contact yield to Aluminum (Al) dual damascene levels is often limited by Al compounds, such as AlOx, which are created at the bottom of a via as a combination of subsequent process steps on the chemically unstable Al surface left by a chemical mechanical polish (CMP) process. These process steps typically include insulator deposition, reactive ion etch (RIE) during the via (over)etch, resist ashing, and chemical wet cleans. These compounds and/or residuals are also hard to remove in a pre-metal deposition sputter clean which often results in bad yields. Another problem with damascene structures is that there is no redundant conductor on top of the Al lines; the lack of a redundant conductor may degrade the reliability of the interconnect.
Back-end-of-line (BEOL) metallization schemes to realize interconnects in integrated circuits (ICs) can be realized by subtractive methods or damascene methods. In subtractive methods, a blanket metal film is patterned via photo lithography and etching. The metal film is usually a stack consisting of a low-resistivity material, such as aluminum sandwiched between barrier and liner metals such as titanium, titanium nitride or a combination of both. The resulting spaces between the lines are later filled with a dielectric.
In the case of damascene methods, a dielectric is deposited first as a blanket film. Trenches are then generated via lithography and etching techniques. These are filled with metal, again usually a stack of different types, which is then polished back to the surface of the dielectric (CMP). Typically, some overpolish is performed to ensure that there are no shorts through remaining metal between the lines. The damascene process can be easily broadened to a dual damascene process by subsequently forming vias to a lower level and trenches to hold an interconnect of a level to be realized. The vias and trenches are formed in a same blanket dielectric film prior to metal deposition and CMP processes. Dual damascene processes are typically less expensive due to the reduction of process steps. In addition, as ground rules continue to shrink, it is easier to etch dielectrics, such as, silicon oxide than it is to etch metal stacks.
Another difference between a damascene and a subtractive metallization method is that the damascene method leaves a polished surface of Al or AlCu behind which is far more reactive than Ti or TiN. This lack of a redundant conductor may degrade the reliability of the interconnect.
Because of the fact that a damascene scheme ends with a CMP step which leaves a rather reactive surface behind as described above, the next contact level needs to form a good and reliable interface with this critical surface. This is independent of the type of interconnect chosen, whether it be another dual damascene level, a stud process, or a tapered via process. The quality of the interface will depend strongly on the local composition of the polished surface. The smaller the vias get, the larger the local variations become due to effects like, for example, copper (Cu) segregation or different degrees of local oxidation. Residuals or compounds formed in the via etch process may also contribute to these effects. These effects are difficult to control or eliminate with cleaning steps.
Referring to
FIG. 1
, a dielectric layer
12
is patterned to form a via
14
and a trench
16
. Via
14
and trench are filled with a metal, such as Al. Another dielectric layer
18
is deposited and patterned to form a via
20
. During patterning of via
20
, a portion
22
of Al oxidizes. This oxidation is particularly difficult to clean. When another conductive material
26
, such as Al, is deposited, the interface between material
26
and an interconnect
24
includes an oxide therebetween which increases resistance, reduces yield and decreases reliability.
Therefore, a need exists for a more reliable and better controlled interface between levels of metal connections.
SUMMARY OF THE INVENTION
A method for connecting metal structures with self-aligned metal caps, in accordance with the invention, includes providing a metal structure in a first dielectric layer. The metal structure and the first dielectric layer share a substantially planar surface. A cap metal is selectively deposited on the metal structure such that the cap metal is deposited only on the metal structure. A second dielectric layer is formed over the cap metal. The second dielectric layer is opened to form a via terminating in the cap metal. A conductive material is deposited in the via to provide a contact to the metal structure through the cap metal.
In alternate methods, the metal structure may include aluminum or copper, and the cap metal may include tungsten. The contact may include aluminum or copper. The step of cleaning the cap metal through the via may be included. The cap metal may include a thickness of between about 300 Å to about 500 Å.
Another method for connecting metal structures with self-aligned metal caps, in accordance with the invention, includes providing a metal structure in a first dielectric layer. The metal structure and the first dielectric layer share a substantially planar surface. A refractory metal is deposited on the metal structure and the first dielectric layer. An alloy is formed between the metal structure and the refractory metal such that the alloy only forms on the substantially planar surface over the metal structure. The refractory metal is removed to the first dielectric layer such that a portion of the alloy remains with the metal structure. A second dielectric layer is formed over the alloy. The second dielectric layer is opened to form a via terminating in the alloy. A conductive material is deposited in the via to provide a contact to the metal structure through the alloy.
In alternate methods, the metal structure may include aluminum or copper. The refractory metal may include titanium, magnesium, nickel, tantalum, hafnium, and/or niobium. The contact may include aluminum or copper. The step of cleaning the cap metal through the via may be included. The cap metal may include a thickness of between about 300 Å to about 500 Å. The step of forming an alloy may include the step of sintering to greater than about 405° C. The step of removing the refractory metal may include etching the refractory metal with an etchant. The step of removing the refractory metal may include polishing the refractory metal.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.


REFERENCES:
patent: 5305519 (1994-04-01), Yamamoto et al.
patent: 5759915 (1998-06-01), Matsunaga et al.
patent: 6066558 (2000-05-01), Kawano et al.

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