Method to form MOSFET with an elevated source/drain for PMOSFET

Details Method to form MOSFET with an elevated source/drain for PMOSFET Method to form MOSFET with an elevated source/drain for PMOSFET

1999-04-30

2001-01-23

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S303000, C438S304000, C438S370000, C257S067000, C257S411000

Reexamination Certificate

active

06177323

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to the manufacturing of transistors in the semiconductor fabrication, and more specifically, to a method of forming a metal oxide semiconductor field effect transistor (MOSFET) having an elevated source/drain for PMOSFETs (p-type MOSFETs).
BACKGROUND OF THE INVENTION
From the first invention of integrated circuits in 1960, the number of devices on a chip has grown at an explosively increasing rate. The technologies of the semiconductor industry has been researched continuously for almost four decades. The progress of the semiconductor integrated circuits has stepped into the ULSI (ultra large scale integration) level or even a higher level. The capacity of a single semiconductor chip increased from several thousand devices to hundreds of million devices, or even to billions of devices. The integrated circuit devices like the transistors, the capacitors, and the connections must be greatly narrowed simultaneously. The increasing packing density of the integrated circuits has generated numerous challenges to the semiconductor manufacturing process. Every device needs to be formed within a smaller size without damaging the characteristics and operations. The demands of high packing density, low heat generation, and low power consumption devices with good reliability and long operation life must be maintained without any degradation in their functions. These achievements are expected to be reached with the five key aspects of the semiconductor manufacturing, including photography, etching, deposition, ion implantation, and thermal processing technologies. The continuous increase in the packing density of the integration circuits must be accompanied with a smaller feature size. With the present semiconductor manufacturing technology, the processes with generally a quarter micrometer in size is widely utilized. For making the next generation devices, the technologies focusing mainly on one-tenth micrometer and even nanometer feature sizes are highly required.
Transistors, or more particularly the metal oxide semiconductor field effect transistors (MOSFET), are the most important and frequently employed devices. The MOSFET is widely employed in the integrated circuits with its high performance. However, with the continuous narrowing of device size, sub-micron scale MOS transistors have to face many risky challenges. As MOS transistors become narrower and thinner accompanied by shorter channels, problems like junction punchthrough, leakage, and contact resistance cause the reduction in the yield and the reliability of the semiconductor manufacturing processes.
For developing future MOS devices with a sub-micrometer or even smaller feature size, the ultra shallow junctions are required to suppress the short channel effects encountered with the down scaling sizes. On the other hand, new challenges arise with a narrowed size. The preparation of an extremely shallow source/drain junction is much harder. The conventional ion implantation process is unable to form a shallow junction with high dopant concentration. In the work by K. Takeuchi et al. (“High Performance Sub-tenth Micron CMOS using Advanced Boron Doping and WSi
2
Dual Gate Process”, 1995 Symposium on VLSI technology Digest of Technical Papers), the problem is addressed. The ion implantation is hard to form shallow and high concentration source/drain. The defect-induced anomalous diffusion of boron in the channel region becomes a problem. Local boron depletion near the source/drain junctions will directly enhance short channel effects. A CMOS fabrication method is also disclosed in their work.
In addition, a device degradation problem is found to come from the boron penetration into the thin gate oxide with the formation of a doped polysilicon gate. S. L. Wu (the inventor of the present invention), C. L. Lee, and T. F. Lai consider the problem in their work “Suppression of Boron Penetration into an Ultra-Thin Gate Oxide (≦7 nm) by Using a Stacked-Amorphous-Silicon (SAS) Film” (IEDM 93329 1993 IEEE). The p+ polysilicon has been widely used as the gate material of pMOSFET to avoid short-channel effects. The BF
2
-implant is typically used in forming both the gate and the junction. However, the F-incorporation will enhance the boron penetration through the thin gate oxide into the silicon substrate. The penetration also results in a large threshold voltage shift. An SAS gate structure is proposed to suppress the F-incorporation-induced boron penetration effect in their work.
SUMMARY OF THE INVENTION
A method of forming a metal oxide semiconductor field effect transistor (MOSFET) with an elevated source/drain is provided in the present invention. The short channel effects can be suppressed with the elevated junction. The boron penetration problem is minimized by the protection of a dielectric layer. An extended ultra-shallow source/drain junction is formed by using a spacer structure as a diffusion source. The effects accompanied by the small feature size devices are eliminated by the extended ultra-shallow junction.
The method of the present invention in forming a transistor, more specifically a MOSFET, on a semiconductor substrate includes the following steps. A gate insulator layer is formed over the semiconductor substrate and a first silicon layer is then formed over the gate insulator layer. An anti-reflection layer is formed over the first silicon layer. A gate region is defined by removing a portion of the gate insulator layer, of the first silicon layer, and of the anti-reflection layer. A portion of the gate insulator layer is removed to have undercut spaces under the first silicon layer. A dielectric layer is then formed on the semiconductor substrate, on the sidewalls of the gate region, and within the undercut spaces. A spacer structure containing first type dopants is then formed on the gate region. Following the removal of the anti-reflection layer, a second silicon layer containing second type dopants is formed over the semiconductor substrate and the first silicon layer. Finally, a thermal process is performed to the semiconductor substrate for diffusing the first type dopants and the second type dopants into the semiconductor substrate.


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